Home
last modified time | relevance | path

Searched refs:dst_h (Results 1 – 25 of 35) sorted by relevance

12

/drivers/media/platform/ti-vpe/
Dsc.c111 unsigned int dst_h) in sc_set_vs_coeffs() argument
119 if (dst_h > src_h) { in sc_set_vs_coeffs()
121 } else if (dst_h == src_h) { in sc_set_vs_coeffs()
124 sixteenths = (dst_h << 4) / src_h; in sc_set_vs_coeffs()
149 unsigned int dst_w, unsigned int dst_h) in sc_config_scaler() argument
178 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
213 if (dst_h < (src_h >> 2)) { in sc_config_scaler()
222 factor = (u16) ((dst_h << 10) / src_h); in sc_config_scaler()
238 src_h, dst_h, factor, row_acc_init_rav, in sc_config_scaler()
242 row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1); in sc_config_scaler()
[all …]
Dsc.h202 unsigned int dst_h);
205 unsigned int dst_w, unsigned int dst_h);
/drivers/media/pci/ivtv/
Divtv-yuv.c390 f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y); in ivtv_yuv_handle_vertical()
420 reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y); in ivtv_yuv_handle_vertical()
422 reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1); in ivtv_yuv_handle_vertical()
425 reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1); in ivtv_yuv_handle_vertical()
427 reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv); in ivtv_yuv_handle_vertical()
429 reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
430 reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
432 if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) { in ivtv_yuv_handle_vertical()
433 master_height = (f->src_h * 0x00400000) / f->dst_h; in ivtv_yuv_handle_vertical()
434 if ((f->src_h * 0x00400000) - (master_height * f->dst_h) >= f->dst_h / 2) in ivtv_yuv_handle_vertical()
[all …]
/drivers/gpu/drm/zte/
Dzx_plane.c150 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
159 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_vl_rsz_setup()
176 zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); in zx_vl_rsz_setup()
178 zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h)); in zx_vl_rsz_setup()
198 u32 dst_x, dst_y, dst_w, dst_h; in zx_vl_plane_atomic_update() local
216 dst_h = drm_rect_height(dst); in zx_vl_plane_atomic_update()
237 GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h)); in zx_vl_plane_atomic_update()
252 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
346 u32 dst_w, u32 dst_h) in zx_gl_rsz_setup() argument
351 zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1)); in zx_gl_rsz_setup()
[all …]
/drivers/gpu/drm/sti/
Dsti_hqvdp.c480 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
520 dst_h = c->hvsrc.output_picture_size >> 16; in hqvdp_dbg_dump_cmd()
521 seq_printf(s, "\t%dx%d", dst_w, dst_h); in hqvdp_dbg_dump_cmd()
540 if (dst_h > src_h) in hqvdp_dbg_dump_cmd()
541 seq_printf(s, " %d/1", dst_h / src_h); in hqvdp_dbg_dump_cmd()
543 seq_printf(s, " 1/%d", src_h / dst_h); in hqvdp_dbg_dump_cmd()
735 int dst_w, int dst_h) in sti_hqvdp_check_hw_scaling() argument
743 inv_zy = DIV_ROUND_UP(src_h, dst_h); in sti_hqvdp_check_hw_scaling()
1030 int dst_x, dst_y, dst_w, dst_h; in sti_hqvdp_atomic_check() local
1042 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); in sti_hqvdp_atomic_check()
[all …]
Dsti_vid.c147 int dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y); in sti_vid_commit() local
154 dst_h = ALIGN(dst_h, 2); in sti_vid_commit()
162 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); in sti_vid_commit()
Dsti_gdp.c629 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_check() local
643 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y); in sti_gdp_atomic_check()
695 dst_w, dst_h, dst_x, dst_y, in sti_gdp_atomic_check()
713 int dst_x, dst_y, dst_w, dst_h; in sti_gdp_atomic_update() local
757 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y); in sti_gdp_atomic_update()
793 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); in sti_gdp_atomic_update()
795 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1); in sti_gdp_atomic_update()
Dsti_cursor.c194 int dst_x, dst_y, dst_w, dst_h; in sti_cursor_atomic_check() local
207 dst_h = clamp_val(new_plane_state->crtc_h, 0, in sti_cursor_atomic_check()
253 DRM_DEBUG_KMS("(%dx%d)@(%d,%d)\n", dst_w, dst_h, dst_x, dst_y); in sti_cursor_atomic_check()
/drivers/gpu/drm/meson/
Dmeson_plane.c147 int src_w, src_h, dst_w, dst_h; in meson_plane_atomic_update() local
266 dst_h = new_state->crtc_h; in meson_plane_atomic_update()
278 dst_h /= 2; in meson_plane_atomic_update()
282 vf_phase_step = (src_h << 20) / dst_h; in meson_plane_atomic_update()
292 if (src_h != dst_h || src_w != dst_w) { in meson_plane_atomic_update()
309 if (src_h != dst_h) { in meson_plane_atomic_update()
362 priv->viu.osb_blend0_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
363 priv->viu.osb_blend1_size = dst_h << 16 | dst_w; in meson_plane_atomic_update()
/drivers/media/platform/rockchip/rga/
Drga-hw.c166 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y; in rga_cmd_set_trans_info() local
184 dst_h = ctx->out.crop.height; in rga_cmd_set_trans_info()
264 if (abs(src_w - dst_h) < 16) in rga_cmd_set_trans_info()
269 scale_dst_w = dst_h; in rga_cmd_set_trans_info()
272 scale_dst_h = dst_h; in rga_cmd_set_trans_info()
312 dst_act_info.data.act_height = dst_h - 1; in rga_cmd_set_trans_info()
324 offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h); in rga_cmd_set_trans_info()
/drivers/gpu/drm/sun4i/
Dsun8i_vi_layer.c105 u32 src_w, src_h, dst_w, dst_h; in sun8i_vi_layer_update_coord() local
122 dst_h = drm_rect_height(&state->dst); in sun8i_vi_layer_update_coord()
147 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_vi_layer_update_coord()
182 required = src_h * 100 / dst_h; in sun8i_vi_layer_update_coord()
187 vn = (u32)ability * dst_h / 100; in sun8i_vi_layer_update_coord()
202 vscale = (src_h << 16) / dst_h; in sun8i_vi_layer_update_coord()
205 dst_h, hscale, vscale, hphase, vphase, in sun8i_vi_layer_update_coord()
233 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_vi_layer_update_coord()
Dsun8i_ui_layer.c101 u32 src_w, src_h, dst_w, dst_h; in sun8i_ui_layer_update_coord() local
115 dst_h = drm_rect_height(&state->dst); in sun8i_ui_layer_update_coord()
121 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); in sun8i_ui_layer_update_coord()
128 dst_w, dst_h); in sun8i_ui_layer_update_coord()
173 dst_h, hscale, vscale, hphase, vphase); in sun8i_ui_layer_update_coord()
183 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); in sun8i_ui_layer_update_coord()
Dsun8i_ui_scaler.c149 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_ui_scaler_setup() argument
167 outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h); in sun8i_ui_scaler_setup()
Dsun8i_vi_scaler.c927 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_vi_scaler_setup() argument
943 outsize = SUN8I_VI_SCALER_SIZE(dst_w, dst_h); in sun8i_vi_scaler_setup()
Dsun8i_ui_scaler.h40 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
Dsun8i_vi_scaler.h74 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
/drivers/gpu/drm/i915/display/
Dskl_scaler.c93 int src_w, int src_h, int dst_w, int dst_h, in skl_update_scaler() argument
109 if (src_w != dst_w || src_h != dst_h) in skl_update_scaler()
159 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || in skl_update_scaler()
162 dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || in skl_update_scaler()
165 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { in skl_update_scaler()
170 dst_w, dst_h); in skl_update_scaler()
178 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, in skl_update_scaler()
Dintel_atomic_plane.c143 unsigned int src_w, src_h, dst_w, dst_h; in intel_adjusted_rate() local
148 dst_h = drm_rect_height(dst); in intel_adjusted_rate()
152 dst_h = min(src_h, dst_h); in intel_adjusted_rate()
155 dst_w * dst_h); in intel_adjusted_rate()
/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.h357 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, in scl_get_bili_dn_vskip() argument
364 if (act_height == dst_h) in scl_get_bili_dn_vskip()
365 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines; in scl_get_bili_dn_vskip()
367 return GET_SCL_FT_BILI_DN(act_height, dst_h); in scl_get_bili_dn_vskip()
/drivers/gpu/drm/
Ddrm_rect.c209 int dst_h = drm_rect_height(dst); in drm_rect_calc_vscale() local
210 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale()
212 if (vscale < 0 || dst_h == 0) in drm_rect_calc_vscale()
/drivers/gpu/drm/imx/dcss/
Ddcss-plane.c278 u32 src_w, src_h, dst_w, dst_h; in dcss_plane_atomic_update() local
304 dst_h = drm_rect_height(&dst); in dcss_plane_atomic_update()
330 dst_w, dst_h, in dcss_plane_atomic_update()
334 dst.x1, dst.y1, dst_w, dst_h); in dcss_plane_atomic_update()
/drivers/media/platform/sti/bdisp/
Dbdisp-hw.c630 u32 src_w, src_h, dst_w, dst_h; in bdisp_hw_get_hv_inc() local
635 dst_h = ctx->dst.crop.height; in bdisp_hw_get_hv_inc()
638 bdisp_hw_get_inc(src_h, dst_h, v_inc)) { in bdisp_hw_get_hv_inc()
641 src_w, src_h, dst_w, dst_h); in bdisp_hw_get_hv_inc()
/drivers/gpu/drm/exynos/
Dexynos_drm_gsc.c747 u32 src_w, src_h, dst_w, dst_h; in gsc_set_prescaler() local
755 dst_h = dst->w; in gsc_set_prescaler()
758 dst_h = dst->h; in gsc_set_prescaler()
767 ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio); in gsc_set_prescaler()
777 sc->main_vratio = (src_h << 16) / dst_h; in gsc_set_prescaler()
Dexynos_drm_fimc.c744 u32 src_w, src_h, dst_w, dst_h; in fimc_set_prescaler() local
757 dst_h = dst->w; in fimc_set_prescaler()
760 dst_h = dst->h; in fimc_set_prescaler()
770 vfactor = fls(src_h / dst_h / 2); in fimc_set_prescaler()
784 sc->vratio = (src_h << 14) / (dst_h << vfactor); in fimc_set_prescaler()
786 sc->up_v = (dst_h >= src_h) ? true : false; in fimc_set_prescaler()
/drivers/gpu/drm/tegra/
Dplane.c254 unsigned int i, bpp, dst_w, dst_h, src_w, src_h, mul; in tegra_plane_calculate_memory_bandwidth() local
270 dst_h = drm_rect_height(&state->dst); in tegra_plane_calculate_memory_bandwidth()
296 avg_bandwidth = min(src_w, dst_w) * min(src_h, dst_h); in tegra_plane_calculate_memory_bandwidth()

12