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Searched refs:enable_bit (Results 1 – 25 of 40) sorted by relevance

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/drivers/clk/ti/
Dclkt_dflt.c154 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
180 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
230 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
232 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
260 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
262 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
287 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
289 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dinterface.c52 clk_hw->enable_bit = bit_idx; in _register_interface()
75 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
83 enable_bit = val; in _of_ti_interface_clk_setup()
93 enable_bit, ops); in _of_ti_interface_clk_setup()
Dgate.c116 clk_hw->enable_bit = bit_idx; in _register_gate()
142 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
152 enable_bit = val; in _of_ti_gate_clk_setup()
170 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
192 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dclkt_iclk.c37 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
52 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
75 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dclk-3xxx.c161 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
184 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
185 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
187 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclkctrl.c155 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
161 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
185 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
218 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
352 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
674 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
676 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
/drivers/clk/
Dclk-max9485.c73 u8 enable_bit; member
115 clk_hw->enable_bit, in max9485_clk_prepare()
116 clk_hw->enable_bit); in max9485_clk_prepare()
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); in max9485_clk_unprepare()
206 u8 enable_bit; member
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
322 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; in max9485_i2c_probe()
/drivers/regulator/
Dtps6586x-regulator.c59 int enable_bit[2]; member
128 .enable_bit[0] = (ebit0), \
130 .enable_bit[1] = (ebit1),
153 .enable_bit[0] = (ebit0), \
155 .enable_bit[1] = (ebit1),
274 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
285 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
292 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
294 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
300 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx.h16 int enable_bit; member
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dmc13xxx-regulator-core.c36 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
37 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
49 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
63 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c330 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
355 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
380 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x-regulator.c82 int enable_bit; member
141 1 << info->enable_bit); in da903x_enable()
150 1 << info->enable_bit); in da903x_disable()
164 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
326 .enable_bit = (ebit), \
348 .enable_bit = (ebit), \
Dmc13892-regulator.c337 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
338 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
362 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
364 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
386 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
Danatop-regulator.c290 u32 enable_bit; in anatop_regulator_probe() local
295 &enable_bit)) { in anatop_regulator_probe()
301 rdesc->enable_mask = BIT(enable_bit); in anatop_regulator_probe()
/drivers/clk/renesas/
Dclk-sh73a0.c92 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
95 switch (enable_bit) { in sh73a0_cpg_register_clock()
111 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
114 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/drivers/sh/clk/
Dcpg.c41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
56 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
61 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
70 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
140 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/drivers/xen/xen-pciback/
Dconf_space_capability.c193 u16 enable_bit; /* bit for enabling MSI/MSI-X */ member
197 .enable_bit = PCI_MSI_FLAGS_ENABLE,
201 .enable_bit = PCI_MSIX_FLAGS_ENABLE,
238 if (new_value & field_config->enable_bit) { in msi_msix_flags_write()
/drivers/clk/ingenic/
Dx1830-cgu.c130 .enable_bit = 0,
153 .enable_bit = 0,
176 .enable_bit = 0,
199 .enable_bit = 0,
Djz4760-cgu.c110 .enable_bit = 8,
134 .enable_bit = 7,
Dx1000-cgu.c202 .enable_bit = 8,
225 .enable_bit = 7,
/drivers/watchdog/
DiTCO_wdt.c153 u32 enable_bit; in no_reboot_bit() local
158 enable_bit = 0x00000010; in no_reboot_bit()
161 enable_bit = 0x00000020; in no_reboot_bit()
166 enable_bit = 0x00000002; in no_reboot_bit()
170 return enable_bit; in no_reboot_bit()
/drivers/tty/serial/
Dmsm_serial.c165 u32 enable_bit; member
260 val &= ~dma->enable_bit; in msm_stop_dma()
320 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; in msm_request_tx_dma()
322 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; in msm_request_tx_dma()
367 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; in msm_request_rx_dma()
369 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; in msm_request_rx_dma()
444 val &= ~dma->enable_bit; in msm_complete_tx_dma()
514 val |= dma->enable_bit; in msm_handle_tx_dma()
548 val &= ~dma->enable_bit; in msm_complete_rx_dma()
649 val |= dma->enable_bit; in msm_start_rx_dma()
/drivers/clk/spear/
Dclk-aux-synth.c41 .enable_bit = AUX_SYNT_ENB,
182 aux->masks->enable_bit, 0, lock); in clk_register_aux()
/drivers/perf/
Dxgene_pmu.c1464 int enable_bit; in acpi_get_pmu_hw_inf() local
1502 enable_bit = 0; in acpi_get_pmu_hw_inf()
1504 enable_bit = (int) obj->integer.value; in acpi_get_pmu_hw_inf()
1506 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); in acpi_get_pmu_hw_inf()
1514 inf->enable_mask = 1 << enable_bit; in acpi_get_pmu_hw_inf()
1633 int enable_bit; in fdt_get_pmu_hw_inf() local
1651 if (of_property_read_u32(np, "enable-bit-index", &enable_bit)) in fdt_get_pmu_hw_inf()
1652 enable_bit = 0; in fdt_get_pmu_hw_inf()
1654 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit); in fdt_get_pmu_hw_inf()
1663 inf->enable_mask = 1 << enable_bit; in fdt_get_pmu_hw_inf()
/drivers/clk/bcm/
Dclk-kona.c272 u32 enable_bit; in __ccu_policy_engine_stop() local
281 enable_bit = enable->bit; in __ccu_policy_engine_stop()
282 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()
290 __ccu_write(ccu, offset, (u32)1 << enable_bit); in __ccu_policy_engine_stop()
293 ret = __ccu_wait_bit(ccu, offset, enable_bit, false); in __ccu_policy_engine_stop()

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