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Searched refs:eqe (Results 1 – 25 of 46) sorted by relevance

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/drivers/net/ethernet/mellanox/mlx4/
Deq.c123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw() local
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
129 struct mlx4_eqe *eqe = in next_slave_event_eqe() local
131 return (!!(eqe->owner & 0x80) ^ in next_slave_event_eqe()
133 eqe : NULL; in next_slave_event_eqe()
146 struct mlx4_eqe *eqe; in mlx4_gen_slave_eqe() local
150 for (eqe = next_slave_event_eqe(slave_eq); eqe; in mlx4_gen_slave_eqe()
151 eqe = next_slave_event_eqe(slave_eq)) { in mlx4_gen_slave_eqe()
152 slave = eqe->slave_id; in mlx4_gen_slave_eqe()
154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE && in mlx4_gen_slave_eqe()
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/drivers/infiniband/hw/mthca/
Dmthca_eq.c236 struct mthca_eqe *eqe; in next_eqe_sw() local
237 eqe = get_eqe(eq, eq->cons_index); in next_eqe_sw()
238 return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe; in next_eqe_sw()
241 static inline void set_eqe_hw(struct mthca_eqe *eqe) in set_eqe_hw() argument
243 eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW; in set_eqe_hw()
262 struct mthca_eqe *eqe; in mthca_eq_int() local
267 while ((eqe = next_eqe_sw(eq))) { in mthca_eq_int()
274 switch (eqe->type) { in mthca_eq_int()
276 disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; in mthca_eq_int()
282 mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, in mthca_eq_int()
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/drivers/net/ethernet/mellanox/mlx5/core/
Deq.c110 struct mlx5_eqe *eqe; in mlx5_eq_comp_int() local
114 eqe = next_eqe_sw(eq); in mlx5_eq_comp_int()
115 if (!eqe) in mlx5_eq_comp_int()
126 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; in mlx5_eq_comp_int()
131 cq->comp(cq, eqe); in mlx5_eq_comp_int()
140 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq))); in mlx5_eq_comp_int()
202 struct mlx5_eqe *eqe; in mlx5_eq_async_int() local
213 eqe = next_eqe_sw(eq); in mlx5_eq_async_int()
214 if (!eqe) in mlx5_eq_async_int()
224 atomic_notifier_call_chain(&eqt->nh[eqe->type], eqe->type, eqe); in mlx5_eq_async_int()
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Devents.c146 struct mlx5_eqe *eqe = data; in any_notifier() local
149 eqe_type_str(eqe->type), eqe->sub_type); in any_notifier()
158 struct mlx5_eqe *eqe = data; in temp_warn() local
162 value_lsb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_lsb); in temp_warn()
163 value_msb = be64_to_cpu(eqe->data.temp_warning.sensor_warning_msb); in temp_warn()
220 struct mlx5_eqe *eqe = data; in port_module() local
228 module_event_eqe = &eqe->data.port_module; in port_module()
311 struct mlx5_eqe *eqe = data; in pcie_core() local
313 switch (eqe->sub_type) { in pcie_core()
334 struct mlx5_eqe *eqe = data; in forward_event() local
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Dfw_reset.c364 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe) in mlx5_sync_reset_events_handle() argument
369 sync_fw_update_eqe = &eqe->data.sync_fw_update; in mlx5_sync_reset_events_handle()
387 struct mlx5_eqe *eqe = data; in fw_reset_event_notifier() local
389 switch (eqe->sub_type) { in fw_reset_event_notifier()
394 mlx5_sync_reset_events_handle(fw_reset, eqe); in fw_reset_event_notifier()
Dpagealloc.c576 struct mlx5_eqe *eqe; in req_pages_handler() local
584 eqe = data; in req_pages_handler()
586 func_id = be16_to_cpu(eqe->data.req_pages.func_id); in req_pages_handler()
587 npages = be32_to_cpu(eqe->data.req_pages.num_pages); in req_pages_handler()
588 ec_function = be16_to_cpu(eqe->data.req_pages.ec_function) & EC_FUNCTION_MASK; in req_pages_handler()
589 release_all = be16_to_cpu(eqe->data.req_pages.ec_function) & in req_pages_handler()
Den_txrx.c247 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) in mlx5e_completion_event() argument
/drivers/net/ethernet/mellanox/mlxsw/
Dpci_hw.h302 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
309 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
314 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
319 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
324 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
329 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
334 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
339 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
Dpci.c766 static void mlxsw_pci_eq_cmd_event(struct mlxsw_pci *mlxsw_pci, char *eqe) in mlxsw_pci_eq_cmd_event() argument
768 mlxsw_pci->cmd.comp.status = mlxsw_pci_eqe_cmd_status_get(eqe); in mlxsw_pci_eq_cmd_event()
770 ((u64) mlxsw_pci_eqe_cmd_out_param_h_get(eqe)) << 32 | in mlxsw_pci_eq_cmd_event()
771 mlxsw_pci_eqe_cmd_out_param_l_get(eqe); in mlxsw_pci_eq_cmd_event()
798 char *eqe; in mlxsw_pci_eq_tasklet() local
806 while ((eqe = mlxsw_pci_eq_sw_eqe_get(q))) { in mlxsw_pci_eq_tasklet()
814 mlxsw_pci_eq_cmd_event(mlxsw_pci, eqe); in mlxsw_pci_eq_tasklet()
818 cqn = mlxsw_pci_eqe_cqn_get(eqe); in mlxsw_pci_eq_tasklet()
/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcore.c164 static int fpga_err_event(struct notifier_block *nb, unsigned long event, void *eqe) in fpga_err_event() argument
168 return mlx5_fpga_event(fdev, event, eqe); in fpga_err_event()
171 static int fpga_qp_err_event(struct notifier_block *nb, unsigned long event, void *eqe) in fpga_qp_err_event() argument
175 return mlx5_fpga_event(fdev, event, eqe); in fpga_qp_err_event()
335 unsigned long event, void *eqe) in mlx5_fpga_event() argument
337 void *data = ((struct mlx5_eqe *)eqe)->data.raw; in mlx5_fpga_event()
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Deq.h63 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & eq->fbc.sz_m1); in next_eqe_sw() local
65 return (eqe->owner ^ (eq->cons_index >> eq->fbc.log_sz)) & 1 ? NULL : eqe; in next_eqe_sw()
Dclock.c729 struct mlx5_eqe *eqe = data; in mlx5_pps_event() local
730 int pin = eqe->data.pps.pin; in mlx5_pps_event()
742 be64_to_cpu(eqe->data.pps.time_stamp)) : in mlx5_pps_event()
744 be64_to_cpu(eqe->data.pps.time_stamp)); in mlx5_pps_event()
/drivers/infiniband/hw/vmw_pvrdma/
Dpvrdma_main.c413 struct pvrdma_eqe *eqe; in pvrdma_intr1_handler() local
415 eqe = get_eqe(dev, head); in pvrdma_intr1_handler()
417 switch (eqe->type) { in pvrdma_intr1_handler()
426 pvrdma_qp_event(dev, eqe->info, eqe->type); in pvrdma_intr1_handler()
430 pvrdma_cq_event(dev, eqe->info, eqe->type); in pvrdma_intr1_handler()
435 pvrdma_srq_event(dev, eqe->info, eqe->type); in pvrdma_intr1_handler()
445 pvrdma_dev_event(dev, eqe->info, eqe->type); in pvrdma_intr1_handler()
449 pvrdma_dev_event(dev, 1, eqe->type); in pvrdma_intr1_handler()
/drivers/infiniband/hw/mlx4/
Dmad.c63 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.bl… argument
64 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_e… argument
1120 struct mlx4_eqe *eqe) in propagate_pkey_ev() argument
1122 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe), in propagate_pkey_ev()
1123 GET_MASK_FROM_EQE(eqe)); in propagate_pkey_ev()
1181 struct mlx4_eqe *eqe = &(ew->ib_eqe); in handle_port_mgmt_change_event() local
1182 u32 port = eqe->event.port_mgmt_change.port; in handle_port_mgmt_change_event()
1187 switch (eqe->subtype) { in handle_port_mgmt_change_event()
1189 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr); in handle_port_mgmt_change_event()
1194 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid); in handle_port_mgmt_change_event()
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/drivers/infiniband/hw/mlx5/
Dqpc.c99 struct mlx5_eqe *eqe; in rsc_event_notifier() local
104 eqe = data; in rsc_event_notifier()
105 rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; in rsc_event_notifier()
116 eqe = data; in rsc_event_notifier()
117 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; in rsc_event_notifier()
118 rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN); in rsc_event_notifier()
Dodp.c1407 struct mlx5_eqe *eqe; in mlx5_ib_eq_pf_process() local
1410 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { in mlx5_ib_eq_pf_process()
1417 pf_eqe = &eqe->data.page_fault; in mlx5_ib_eq_pf_process()
1418 pfault->event_subtype = eqe->sub_type; in mlx5_ib_eq_pf_process()
1423 eqe->sub_type, pfault->bytes_committed); in mlx5_ib_eq_pf_process()
1425 switch (eqe->sub_type) { in mlx5_ib_eq_pf_process()
1474 eqe->sub_type); in mlx5_ib_eq_pf_process()
Ddevx.c251 static u16 get_event_obj_type(unsigned long event_type, struct mlx5_eqe *eqe) in get_event_obj_type() argument
264 return eqe->data.qp_srq.type; in get_event_obj_type()
272 return MLX5_GET(affiliated_event_header, &eqe->data, obj_type); in get_event_obj_type()
1430 static void devx_cq_comp(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe) in devx_cq_comp() argument
1448 dispatch_event_fd(&obj_event->obj_sub_list, eqe); in devx_cq_comp()
2389 struct mlx5_eqe *eqe = data; in devx_get_obj_id_from_event() local
2403 obj_id = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; in devx_get_obj_id_from_event()
2406 obj_id = be32_to_cpu(eqe->data.xrq_err.type_xrqn) & 0xffffff; in devx_get_obj_id_from_event()
2410 obj_id = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff; in devx_get_obj_id_from_event()
2413 obj_id = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; in devx_get_obj_id_from_event()
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Dsrq_cmd.c728 struct mlx5_eqe *eqe; in srq_event_notifier() local
737 eqe = data; in srq_event_notifier()
738 srqn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; in srq_event_notifier()
749 srq->event(srq, eqe->type); in srq_event_notifier()
/drivers/net/ethernet/ibm/ehea/
Dehea_main.c922 struct ehea_eqe *eqe; in ehea_qp_aff_irq_handler() local
928 eqe = ehea_poll_eq(port->qp_eq); in ehea_qp_aff_irq_handler()
930 while (eqe) { in ehea_qp_aff_irq_handler()
931 qp_token = EHEA_BMASK_GET(EHEA_EQE_QP_TOKEN, eqe->entry); in ehea_qp_aff_irq_handler()
933 eqe->entry, qp_token); in ehea_qp_aff_irq_handler()
947 eqe = ehea_poll_eq(port->qp_eq); in ehea_qp_aff_irq_handler()
1135 static void ehea_parse_eqe(struct ehea_adapter *adapter, u64 eqe) in ehea_parse_eqe() argument
1143 ec = EHEA_BMASK_GET(NEQE_EVENT_CODE, eqe); in ehea_parse_eqe()
1144 portnum = EHEA_BMASK_GET(NEQE_PORTNUM, eqe); in ehea_parse_eqe()
1155 if (EHEA_BMASK_GET(NEQE_PORT_UP, eqe)) { in ehea_parse_eqe()
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Dehea_qmr.c305 struct ehea_eqe *eqe; in ehea_poll_eq() local
309 eqe = hw_eqit_eq_get_inc_valid(&eq->hw_queue); in ehea_poll_eq()
312 return eqe; in ehea_poll_eq()
/drivers/net/ethernet/microsoft/mana/
Dgdma_main.c295 struct gdma_eqe *eqe; in mana_gd_process_eqe() local
298 eqe = &eq_eqe_ptr[head]; in mana_gd_process_eqe()
299 eqe_info.as_uint32 = eqe->eqe_info; in mana_gd_process_eqe()
304 cq_id = eqe->details[0] & 0xFFFFFF; in mana_gd_process_eqe()
329 memcpy(&event.details, &eqe->details, GDMA_EVENT_DATA_SIZE); in mana_gd_process_eqe()
345 struct gdma_eqe *eqe; in mana_gd_process_eq_events() local
356 eqe = &eq_eqe_ptr[eq->head % num_eqe]; in mana_gd_process_eq_events()
357 eqe_info.as_uint32 = eqe->eqe_info; in mana_gd_process_eq_events()
/drivers/net/ethernet/mellanox/mlx5/core/sf/
Dvhca_event.c105 struct mlx5_eqe *eqe = data; in mlx5_vhca_state_change_notifier() local
112 work->event.function_id = be16_to_cpu(eqe->data.vhca_state.function_id); in mlx5_vhca_state_change_notifier()
/drivers/scsi/be2iscsi/
Dbe_main.c667 struct be_eq_entry *eqe; in be_isr_mcc() local
677 eqe = queue_tail_node(eq); in be_isr_mcc()
680 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] in be_isr_mcc()
682 if (((eqe->dw[offsetof(struct amap_eq_entry, in be_isr_mcc()
687 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); in be_isr_mcc()
689 eqe = queue_tail_node(eq); in be_isr_mcc()
731 struct be_eq_entry *eqe; in be_isr() local
752 eqe = queue_tail_node(eq); in be_isr()
756 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] in be_isr()
758 if (((eqe->dw[offsetof(struct amap_eq_entry, in be_isr()
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/drivers/net/ethernet/mellanox/mlx5/core/en/
Dmonitor_stats.c60 unsigned long event, void *eqe) in mlx5e_monitor_event_handler() argument
/drivers/crypto/hisilicon/
Dqm.c87 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1) argument
767 static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe) in qm_to_hisi_qp() argument
769 u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK; in qm_to_hisi_qp()
817 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head; in qm_work_process() local
821 while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) { in qm_work_process()
823 qp = qm_to_hisi_qp(qm, eqe); in qm_work_process()
828 eqe = qm->eqe; in qm_work_process()
831 eqe++; in qm_work_process()
1787 if (qm->eqe && !strcmp(name, "EQE")) { in qm_eq_aeq_dump()
1788 xeqe = qm->eqe + xeqe_id; in qm_eq_aeq_dump()
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