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Searched refs:factors (Results 1 – 12 of 12) sorted by relevance

/drivers/clk/sunxi/
Dclk-factors.c46 struct clk_factors *factors = to_clk_factors(hw); in clk_factors_recalc_rate() local
47 const struct clk_factors_config *config = factors->config; in clk_factors_recalc_rate()
50 reg = readl(factors->reg); in clk_factors_recalc_rate()
62 if (factors->recalc) { in clk_factors_recalc_rate()
72 if (factors->mux) in clk_factors_recalc_rate()
74 (reg >> factors->mux->shift) & in clk_factors_recalc_rate()
75 factors->mux->mask; in clk_factors_recalc_rate()
77 factors->recalc(&factors_req); in clk_factors_recalc_rate()
91 struct clk_factors *factors = to_clk_factors(hw); in clk_factors_determine_rate() local
112 factors->get_factors(&factors_req); in clk_factors_determine_rate()
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Dclk-sunxi.c874 const struct factors_data *factors; /* data for the factor clock */ member
902 .factors = &sun4i_pll5_data,
913 .factors = &sun4i_pll5_data,
924 .factors = &sun6i_a31_pll6_data,
955 struct factors_data factors = *data->factors; in sunxi_divs_clk_setup() local
969 i, &factors.name); in sunxi_divs_clk_setup()
974 if (factors.name == NULL) { in sunxi_divs_clk_setup()
985 factors.name = derived_name; in sunxi_divs_clk_setup()
987 factors.name = clk_name; in sunxi_divs_clk_setup()
992 pclk = sunxi_factors_clk_setup(node, &factors); in sunxi_divs_clk_setup()
DMakefile6 obj-$(CONFIG_CLK_SUNXI) += clk-factors.o
/drivers/clk/
Dclk-milbeaut.c498 static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors, in m10v_reg_div_pre() argument
509 if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10))) in m10v_reg_div_pre()
514 hw = m10v_clk_hw_register_divider(NULL, factors->name, in m10v_reg_div_pre()
515 factors->parent_name, in m10v_reg_div_pre()
517 base + factors->offset, in m10v_reg_div_pre()
518 factors->shift, in m10v_reg_div_pre()
519 factors->width, factors->div_flags, in m10v_reg_div_pre()
520 factors->table, in m10v_reg_div_pre()
523 if (factors->onecell_idx >= 0) in m10v_reg_div_pre()
524 clk_data->hws[factors->onecell_idx] = hw; in m10v_reg_div_pre()
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/drivers/staging/media/sunxi/cedrus/
Dcedrus_h264.c276 const struct v4l2_h264_weight_factors *factors = in cedrus_write_pred_weight_table() local
279 for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { in cedrus_write_pred_weight_table()
282 val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | in cedrus_write_pred_weight_table()
283 (factors->luma_weight[j] & 0x1ff); in cedrus_write_pred_weight_table()
287 for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { in cedrus_write_pred_weight_table()
288 for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { in cedrus_write_pred_weight_table()
291 val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | in cedrus_write_pred_weight_table()
292 (factors->chroma_weight[j][k] & 0x1ff); in cedrus_write_pred_weight_table()
/drivers/clk/sprd/
Dpll.h54 const struct clk_bit_field *factors; member
71 .factors = _factors, \
Dpll.c19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
25 pll->factors[member].width
/drivers/staging/media/atomisp/pci/isp/kernels/anr/anr_1.0/
Dia_css_anr_types.h33 s32 factors[3]; member
/drivers/net/wireless/microchip/wilc1000/
Dwlan.c286 u8 factors[NQUEUES] = {1, 1, 1, 1}; in is_ac_q_limit() local
300 q->cnt[i] = AC_BUFFER_SIZE * factors[i] / NQUEUES; in is_ac_q_limit()
308 q->cnt[q->buffer[end_index]] -= factors[q->buffer[end_index]]; in is_ac_q_limit()
309 q->cnt[q_num] += factors[q_num]; in is_ac_q_limit()
310 q->sum += (factors[q_num] - factors[q->buffer[end_index]]); in is_ac_q_limit()
/drivers/net/can/usb/
DKconfig130 adapters from Theobroma Systems. There are two form-factors
/drivers/s390/block/
Ddasd_eckd.h296 } __attribute__ ((packed)) factors; member
/drivers/gpio/
DTODO27 base as -1 in struct gpio_chip) has also became unpredictable due to factors