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/drivers/gpio/
Dgpio-ftgpio010.c59 struct ftgpio_gpio *g = gpiochip_get_data(gc); in ftgpio_gpio_ack_irq() local
61 writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); in ftgpio_gpio_ack_irq()
67 struct ftgpio_gpio *g = gpiochip_get_data(gc); in ftgpio_gpio_mask_irq() local
70 val = readl(g->base + GPIO_INT_EN); in ftgpio_gpio_mask_irq()
72 writel(val, g->base + GPIO_INT_EN); in ftgpio_gpio_mask_irq()
78 struct ftgpio_gpio *g = gpiochip_get_data(gc); in ftgpio_gpio_unmask_irq() local
81 val = readl(g->base + GPIO_INT_EN); in ftgpio_gpio_unmask_irq()
83 writel(val, g->base + GPIO_INT_EN); in ftgpio_gpio_unmask_irq()
89 struct ftgpio_gpio *g = gpiochip_get_data(gc); in ftgpio_gpio_set_irq_type() local
93 reg_type = readl(g->base + GPIO_INT_TYPE); in ftgpio_gpio_set_irq_type()
[all …]
Dgpio-ixp4xx.c65 struct ixp4xx_gpio *g = gpiochip_get_data(gc); in ixp4xx_gpio_irq_ack() local
67 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
73 struct ixp4xx_gpio *g = gpiochip_get_data(gc); in ixp4xx_gpio_irq_unmask() local
76 if (!(g->irq_edge & BIT(d->hwirq))) in ixp4xx_gpio_irq_unmask()
85 struct ixp4xx_gpio *g = gpiochip_get_data(gc); in ixp4xx_gpio_irq_set_type() local
96 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
101 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
106 g->irq_edge |= BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
111 g->irq_edge &= ~BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
116 g->irq_edge &= ~BIT(d->hwirq); in ixp4xx_gpio_irq_set_type()
[all …]
Dgpio-davinci.c74 struct davinci_gpio_regs __iomem *g; in irq2regs() local
76 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); in irq2regs()
78 return g; in irq2regs()
90 struct davinci_gpio_regs __iomem *g; in __davinci_direction() local
96 g = d->regs[bank]; in __davinci_direction()
98 temp = readl_relaxed(&g->dir); in __davinci_direction()
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
105 writel_relaxed(temp, &g->dir); in __davinci_direction()
132 struct davinci_gpio_regs __iomem *g; in davinci_gpio_get() local
135 g = d->regs[bank]; in davinci_gpio_get()
[all …]
Dgpio-bd71815.c132 struct bd71815_gpio *g; in gpo_bd71815_probe() local
143 g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); in gpo_bd71815_probe()
144 if (!g) in gpo_bd71815_probe()
147 g->chip = bd71815gpo_chip; in gpo_bd71815_probe()
160 g->chip.ngpio = 2; in gpo_bd71815_probe()
162 g->chip.ngpio = 1; in gpo_bd71815_probe()
164 g->chip.init_valid_mask = bd71815_init_valid_mask; in gpo_bd71815_probe()
165 g->chip.base = -1; in gpo_bd71815_probe()
166 g->chip.parent = parent; in gpo_bd71815_probe()
167 g->regmap = dev_get_regmap(parent, NULL); in gpo_bd71815_probe()
[all …]
/drivers/pinctrl/qcom/
Dpinctrl-msm.c85 const struct msm_pingroup *g) \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
90 const struct msm_pingroup *g) \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
102 const struct msm_pingroup *g) in MSM_ACCESSOR()
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
106 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
188 const struct msm_pingroup *g; in msm_pinmux_set_mux() local
193 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
194 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); in msm_pinmux_set_mux()
[all …]
/drivers/pinctrl/tegra/
Dpinctrl-tegra.c254 const struct tegra_pingroup *g; in tegra_pinctrl_set_mux() local
258 g = &pmx->soc->groups[group]; in tegra_pinctrl_set_mux()
260 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
263 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { in tegra_pinctrl_set_mux()
264 if (g->funcs[i] == function) in tegra_pinctrl_set_mux()
267 if (WARN_ON(i == ARRAY_SIZE(g->funcs))) in tegra_pinctrl_set_mux()
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
271 val &= ~(0x3 << g->mux_bit); in tegra_pinctrl_set_mux()
272 val |= i << g->mux_bit; in tegra_pinctrl_set_mux()
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
[all …]
/drivers/usb/gadget/udc/
Dtrace.h21 TP_PROTO(struct usb_gadget *g, int ret),
22 TP_ARGS(g, ret),
45 __entry->speed = g->speed;
46 __entry->max_speed = g->max_speed;
47 __entry->state = g->state;
48 __entry->mA = g->mA;
49 __entry->sg_supported = g->sg_supported;
50 __entry->is_otg = g->is_otg;
51 __entry->is_a_peripheral = g->is_a_peripheral;
52 __entry->b_hnp_enable = g->b_hnp_enable;
[all …]
/drivers/staging/most/dim2/
Dhal.c84 static struct lld_global_vars_t g = { false }; variable
120 if ((g.dbr_map[i] & mask) == 0) { in alloc_dbr()
121 g.dbr_map[i] |= mask; in alloc_dbr()
140 g.dbr_map[block_idx / 32] &= ~mask; in free_dbr()
147 writel(val, &g.dim2->MADR); in dim2_transfer_madr()
150 while ((readl(&g.dim2->MCTL) & 1) != 1) in dim2_transfer_madr()
153 writel(0, &g.dim2->MCTL); /* clear transfer complete */ in dim2_transfer_madr()
163 writel(0, &g.dim2->MCTL); /* clear transfer complete */ in dim2_clear_dbr()
164 writel(0, &g.dim2->MDAT0); in dim2_clear_dbr()
174 return readl((&g.dim2->MDAT0) + mdat_idx); in dim2_read_ctr()
[all …]
/drivers/clk/renesas/
Dr9a06g032-clocks.c435 struct r9a06g032_gate *g, int on) in r9a06g032_clk_gate_set() argument
439 WARN_ON(!g->gate); in r9a06g032_clk_gate_set()
442 clk_rdesc_set(clocks, g->gate, on); in r9a06g032_clk_gate_set()
444 if (g->reset) in r9a06g032_clk_gate_set()
445 clk_rdesc_set(clocks, g->reset, 1); in r9a06g032_clk_gate_set()
455 if (g->ready || g->midle) { in r9a06g032_clk_gate_set()
457 if (g->ready) in r9a06g032_clk_gate_set()
458 clk_rdesc_set(clocks, g->ready, on); in r9a06g032_clk_gate_set()
460 if (g->midle) in r9a06g032_clk_gate_set()
461 clk_rdesc_set(clocks, g->midle, !on); in r9a06g032_clk_gate_set()
[all …]
/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main_regs.h81 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) argument
84 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) argument
87 #define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) argument
96 #define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) argument
99 #define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) argument
102 #define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) argument
111 #define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) argument
150 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4) argument
171 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4) argument
246 #define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) argument
[all …]
/drivers/gpu/host1x/
Djob.c139 struct host1x_job_gather *g; in pin_job() local
238 g = &job->cmds[i].gather; in pin_job()
240 g->bo = host1x_bo_get(g->bo); in pin_job()
241 if (!g->bo) { in pin_job()
256 sgt = host1x_bo_pin(host->dev, g->bo, phys); in pin_job()
299 job->unpins[job->num_unpins].bo = g->bo; in pin_job()
307 host1x_bo_put(g->bo); in pin_job()
313 static int do_relocs(struct host1x_job *job, struct host1x_job_gather *g) in do_relocs() argument
316 struct host1x_bo *cmdbuf = g->bo; in do_relocs()
333 g->offset / sizeof(u32); in do_relocs()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dfs_ttc.c32 struct mlx5_flow_group **g; member
296 ttc->g = kcalloc(MLX5_TTC_NUM_GROUPS, sizeof(*ttc->g), GFP_KERNEL); in mlx5_create_ttc_table_groups()
297 if (!ttc->g) in mlx5_create_ttc_table_groups()
301 kfree(ttc->g); in mlx5_create_ttc_table_groups()
302 ttc->g = NULL; in mlx5_create_ttc_table_groups()
317 ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in); in mlx5_create_ttc_table_groups()
318 if (IS_ERR(ttc->g[ttc->num_groups])) in mlx5_create_ttc_table_groups()
327 ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in); in mlx5_create_ttc_table_groups()
328 if (IS_ERR(ttc->g[ttc->num_groups])) in mlx5_create_ttc_table_groups()
337 ttc->g[ttc->num_groups] = mlx5_create_flow_group(ttc->t, in); in mlx5_create_ttc_table_groups()
[all …]
/drivers/pinctrl/freescale/
Dpinctrl-mxs.c204 struct mxs_group *g = &d->soc->groups[group]; in mxs_pinctrl_set_mux() local
210 for (i = 0; i < g->npins; i++) { in mxs_pinctrl_set_mux()
211 bank = PINID_TO_BANK(g->pins[i]); in mxs_pinctrl_set_mux()
212 pin = PINID_TO_PIN(g->pins[i]); in mxs_pinctrl_set_mux()
217 mxs_pinctrl_rmwl(g->muxsel[i], 0x3, shift, reg); in mxs_pinctrl_set_mux()
258 struct mxs_group *g = &d->soc->groups[group]; in mxs_pinconf_group_set() local
273 for (i = 0; i < g->npins; i++) { in mxs_pinconf_group_set()
274 bank = PINID_TO_BANK(g->pins[i]); in mxs_pinconf_group_set()
275 pin = PINID_TO_PIN(g->pins[i]); in mxs_pinconf_group_set()
309 g->config = config; in mxs_pinconf_group_set()
[all …]
/drivers/media/common/v4l2-tpg/
Dv4l2-tpg-colors.c1153 static void mult_matrix(double *r, double *g, double *b, const double m[3][3]) in mult_matrix() argument
1157 ir = m[0][0] * (*r) + m[0][1] * (*g) + m[0][2] * (*b); in mult_matrix()
1158 ig = m[1][0] * (*r) + m[1][1] * (*g) + m[1][2] * (*b); in mult_matrix()
1159 ib = m[2][0] * (*r) + m[2][1] * (*g) + m[2][2] * (*b); in mult_matrix()
1161 *g = ig; in mult_matrix()
1232 double *r, double *g, double *b) in csc() argument
1237 *g = transfer_srgb_to_rgb(*g); in csc()
1243 mult_matrix(r, g, b, rec709_to_240m); in csc()
1246 mult_matrix(r, g, b, rec709_to_170m); in csc()
1249 mult_matrix(r, g, b, rec709_to_ebu); in csc()
[all …]
Dv4l2-tpg-core.c549 static void color_to_hsv(struct tpg_data *tpg, int r, int g, int b, in color_to_hsv() argument
558 g >>= 4; in color_to_hsv()
562 max_rgb = max3(r, g, b); in color_to_hsv()
571 min_rgb = min3(r, g, b); in color_to_hsv()
586 aux = g - b; in color_to_hsv()
588 } else if (max_rgb == g) { in color_to_hsv()
592 aux = r - g; in color_to_hsv()
614 static void rgb2ycbcr(const int m[3][3], int r, int g, int b, in rgb2ycbcr() argument
617 *y = ((m[0][0] * r + m[0][1] * g + m[0][2] * b) >> 16) + (y_offset << 4); in rgb2ycbcr()
618 *cb = ((m[1][0] * r + m[1][1] * g + m[1][2] * b) >> 16) + (128 << 4); in rgb2ycbcr()
[all …]
/drivers/pinctrl/
Dpinctrl-palmas.c575 const struct palmas_pingroup *g; in palmas_pinctrl_get_pin_mux() local
581 g = &pci->pin_groups[i]; in palmas_pinctrl_get_pin_mux()
582 if (g->mux_reg_base == PALMAS_NONE_BASE) { in palmas_pinctrl_get_pin_mux()
586 ret = palmas_read(pci->palmas, g->mux_reg_base, in palmas_pinctrl_get_pin_mux()
587 g->mux_reg_add, &val); in palmas_pinctrl_get_pin_mux()
590 g->mux_reg_add, ret); in palmas_pinctrl_get_pin_mux()
593 val &= g->mux_reg_mask; in palmas_pinctrl_get_pin_mux()
594 pci->pins_current_opt[i] = val >> g->mux_bit_shift; in palmas_pinctrl_get_pin_mux()
693 const struct palmas_pingroup *g; in palmas_pinctrl_set_mux() local
697 g = &pci->pin_groups[group]; in palmas_pinctrl_set_mux()
[all …]
/drivers/gpu/host1x/hw/
Ddebug_hw.c209 struct host1x_job_gather *g; in show_channel_gathers() local
215 g = &job->cmds[i].gather; in show_channel_gathers()
220 mapped = host1x_bo_mmap(g->bo); in show_channel_gathers()
228 &g->base, g->offset, g->words); in show_channel_gathers()
230 show_gather(o, g->base + g->offset, g->words, cdma, in show_channel_gathers()
231 g->base, mapped); in show_channel_gathers()
234 host1x_bo_munmap(g->bo, mapped); in show_channel_gathers()
/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Dingress_lgcy.c23 struct mlx5_flow_group *g; in esw_acl_ingress_lgcy_groups_create() local
42 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in); in esw_acl_ingress_lgcy_groups_create()
43 if (IS_ERR(g)) { in esw_acl_ingress_lgcy_groups_create()
44 err = PTR_ERR(g); in esw_acl_ingress_lgcy_groups_create()
49 vport->ingress.legacy.allow_untagged_spoofchk_grp = g; in esw_acl_ingress_lgcy_groups_create()
58 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in); in esw_acl_ingress_lgcy_groups_create()
59 if (IS_ERR(g)) { in esw_acl_ingress_lgcy_groups_create()
60 err = PTR_ERR(g); in esw_acl_ingress_lgcy_groups_create()
65 vport->ingress.legacy.allow_untagged_only_grp = g; in esw_acl_ingress_lgcy_groups_create()
75 g = mlx5_create_flow_group(vport->ingress.acl, flow_group_in); in esw_acl_ingress_lgcy_groups_create()
[all …]
/drivers/usb/mtu3/
Dmtu3_gadget.c30 usb_gadget_unmap_request(&mtu->g, req, mep->is_in); in mtu3_req_complete()
74 switch (mtu->g.speed) { in mtu3_ep_enable()
298 ret = usb_gadget_map_request(&mtu->g, req, mep->is_in); in mtu3_gadget_queue()
448 if (mtu->g.speed >= USB_SPEED_SUPER) { in mtu3_gadget_wakeup()
506 mtu->g.name, mtu->gadget_driver->driver.name); in mtu3_gadget_start()
533 if (mtu->g.speed == USB_SPEED_UNKNOWN) in stop_activity()
536 mtu->g.speed = USB_SPEED_UNKNOWN; in stop_activity()
556 driver->disconnect(&mtu->g); in stop_activity()
561 static int mtu3_gadget_stop(struct usb_gadget *g) in mtu3_gadget_stop() argument
563 struct mtu3 *mtu = gadget_to_mtu3(g); in mtu3_gadget_stop()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/en/
Dfs_tt_redirect.c155 ft->g = kcalloc(MLX5E_FS_UDP_NUM_GROUPS, sizeof(*ft->g), GFP_KERNEL); in fs_udp_create_groups()
157 if (!in || !ft->g) { in fs_udp_create_groups()
158 kfree(ft->g); in fs_udp_create_groups()
159 ft->g = NULL; in fs_udp_create_groups()
183 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in); in fs_udp_create_groups()
184 if (IS_ERR(ft->g[ft->num_groups])) in fs_udp_create_groups()
193 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in); in fs_udp_create_groups()
194 if (IS_ERR(ft->g[ft->num_groups])) in fs_udp_create_groups()
202 err = PTR_ERR(ft->g[ft->num_groups]); in fs_udp_create_groups()
203 ft->g[ft->num_groups] = NULL; in fs_udp_create_groups()
[all …]
/drivers/pinctrl/actions/
Dpinctrl-owl.c165 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g, in get_group_mfp_mask_val() argument
174 for (id = 0; id < g->nfuncs; id++) { in get_group_mfp_mask_val()
175 if (g->funcs[id] == function) in get_group_mfp_mask_val()
178 if (WARN_ON(id == g->nfuncs)) in get_group_mfp_mask_val()
181 option_num = (1 << g->mfpctl_width); in get_group_mfp_mask_val()
186 *mask = (option_mask << g->mfpctl_shift); in get_group_mfp_mask_val()
187 *val = (id << g->mfpctl_shift); in get_group_mfp_mask_val()
197 const struct owl_pingroup *g; in owl_set_mux() local
201 g = &pctrl->soc->groups[group]; in owl_set_mux()
203 if (get_group_mfp_mask_val(g, function, &mask, &val)) in owl_set_mux()
[all …]
/drivers/gpu/drm/panel/
Dpanel-tpo-td043mtea1.c263 unsigned int g[12]; in gamma_store() local
268 &g[0], &g[1], &g[2], &g[3], &g[4], &g[5], in gamma_store()
269 &g[6], &g[7], &g[8], &g[9], &g[10], &g[11]); in gamma_store()
274 lcd->gamma[i] = g[i]; in gamma_store()
/drivers/gpu/drm/amd/display/modules/color/
Dcolor_gamma.c530 left = axis_x[i].g; in find_software_points()
533 right = axis_x[i + 1].g; in find_software_points()
535 right = axis_x[max_number - 1].g; in find_software_points()
638 point = &coeff[i].g; in build_custom_gamma_mapping_coefficients_worker()
640 left_pos = axis_x[index_left].g; in build_custom_gamma_mapping_coefficients_worker()
641 right_pos = axis_x[index_right].g; in build_custom_gamma_mapping_coefficients_worker()
689 point = &coeff->g; in calculate_mapped_value()
717 rgb[point->right_index].g, in calculate_mapped_value()
718 rgb[point->left_index].g)), in calculate_mapped_value()
719 rgb[point->left_index].g); in calculate_mapped_value()
[all …]
/drivers/md/bcache/
Dextents.c177 struct bucket *g; in btree_ptr_bad_expensive() local
182 g = PTR_BUCKET(b->c, k, i); in btree_ptr_bad_expensive()
185 g->prio != BTREE_PRIO || in btree_ptr_bad_expensive()
187 GC_MARK(g) != GC_MARK_METADATA)) in btree_ptr_bad_expensive()
200 buf, PTR_BUCKET_NR(b->c, k, i), atomic_read(&g->pin), in btree_ptr_bad_expensive()
201 g->prio, g->gen, g->last_gc, GC_MARK(g)); in btree_ptr_bad_expensive()
510 struct bucket *g = PTR_BUCKET(b->c, k, ptr); in bch_extent_bad_expensive() local
515 (!GC_MARK(g) || in bch_extent_bad_expensive()
516 GC_MARK(g) == GC_MARK_METADATA || in bch_extent_bad_expensive()
517 (GC_MARK(g) != GC_MARK_DIRTY && KEY_DIRTY(k)))) in bch_extent_bad_expensive()
[all …]
/drivers/media/i2c/
Dtea6420.c42 int g = (o >> 4) & 0xf; in tea6420_s_routing() local
47 v4l2_dbg(1, debug, sd, "i=%d, o=%d, g=%d\n", i, o, g); in tea6420_s_routing()
50 if (i < 1 || i > 6 || o < 1 || o > 4 || g < 0 || g > 6 || g % 2 != 0) in tea6420_s_routing()
57 switch (g) { in tea6420_s_routing()

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