Searched refs:gpu_offset (Results 1 – 10 of 10) sorted by relevance
1148 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1220 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1232 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1244 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1256 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1280 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1300 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1504 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1521 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()1562 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()[all …]
1022 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1084 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1086 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()1105 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1214 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1245 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1281 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1284 track->cb_color_bo_mc[tmp] = reloc->gpu_offset; in r600_cs_check_reg()1295 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()1297 track->db_bo_mc = reloc->gpu_offset; in r600_cs_check_reg()[all …]
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()228 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r200_packet0_check()230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()274 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()368 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
674 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()687 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()716 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()725 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1086 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1131 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()1197 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r300_packet3_check()
1287 tmp += (((u32)reloc->gpu_offset) >> 10); in r100_reloc_pitch_offset()1338 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1350 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1364 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); in r100_packet3_load_vbpntr()1605 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1618 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1639 ib[idx] = tmp + ((u32)reloc->gpu_offset); in r100_packet0_check()1641 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1659 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()1677 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()[all …]
544 lobj->gpu_offset = radeon_bo_gpu_offset(bo); in radeon_bo_list_validate()549 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); in radeon_bo_list_validate()
878 (*cs_reloc)->gpu_offset = in radeon_cs_packet_next_reloc()880 (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; in radeon_cs_packet_next_reloc()
488 start = reloc->gpu_offset; in radeon_vce_cs_reloc()
594 start = reloc->gpu_offset; in radeon_uvd_cs_reloc()
462 uint64_t gpu_offset; member