| /drivers/gpu/drm/bridge/synopsys/ |
| D | dw-hdmi.c | 138 int (*configure)(struct dw_hdmi *hdmi,
201 void (*enable_audio)(struct dw_hdmi *hdmi);
202 void (*disable_audio)(struct dw_hdmi *hdmi);
220 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) in hdmi_writeb() argument
222 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); in hdmi_writeb()
225 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) in hdmi_readb() argument
229 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); in hdmi_readb()
234 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) in handle_plugged_change() argument
236 if (hdmi->plugged_cb && hdmi->codec_dev) in handle_plugged_change()
237 hdmi->plugged_cb(hdmi->codec_dev, plugged); in handle_plugged_change()
[all …]
|
| /drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi_i2c.c | 25 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) in fifo_transfer() argument
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
59 readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
64 regmap_field_force_write(hdmi->field_ddc_int_status, in fifo_transfer()
70 static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg) in xfer_msg() argument
76 if (hdmi->variant->ddc_fifo_has_dir) { in xfer_msg()
77 reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); in xfer_msg()
82 writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); in xfer_msg()
[all …]
|
| D | sun4i_hdmi_enc.c | 46 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, in sun4i_hdmi_setup_avi_infoframes() argument
54 &hdmi->connector, mode); in sun4i_hdmi_setup_avi_infoframes()
67 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); in sun4i_hdmi_setup_avi_infoframes()
86 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); in sun4i_hdmi_disable() local
91 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); in sun4i_hdmi_disable()
93 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); in sun4i_hdmi_disable()
95 clk_disable_unprepare(hdmi->tmds_clk); in sun4i_hdmi_disable()
101 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); in sun4i_hdmi_enable() local
106 clk_prepare_enable(hdmi->tmds_clk); in sun4i_hdmi_enable()
108 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); in sun4i_hdmi_enable()
[all …]
|
| D | sun8i_dw_hdmi.c | 22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
128 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
134 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in sun8i_dw_hdmi_bind()
135 if (!hdmi) in sun8i_dw_hdmi_bind()
138 plat_data = &hdmi->plat_data; in sun8i_dw_hdmi_bind()
139 hdmi->dev = &pdev->dev; in sun8i_dw_hdmi_bind()
140 encoder = &hdmi->encoder; in sun8i_dw_hdmi_bind()
[all …]
|
| /drivers/gpu/drm/rockchip/ |
| D | rk3066_hdmi.c | 63 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) in hdmi_readb() argument
65 return readl_relaxed(hdmi->regs + offset); in hdmi_readb()
68 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() argument
70 writel_relaxed(val, hdmi->regs + offset); in hdmi_writeb()
73 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, in hdmi_modb() argument
76 u8 temp = hdmi_readb(hdmi, offset) & ~msk; in hdmi_modb()
79 hdmi_writeb(hdmi, offset, temp); in hdmi_modb()
82 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi) in rk3066_hdmi_i2c_init() argument
86 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE; in rk3066_hdmi_i2c_init()
88 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); in rk3066_hdmi_i2c_init()
[all …]
|
| D | inno_hdmi.c | 149 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) in hdmi_readb() argument
151 return readl_relaxed(hdmi->regs + (offset) * 0x04); in hdmi_readb()
154 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() argument
156 writel_relaxed(val, hdmi->regs + (offset) * 0x04); in hdmi_writeb()
159 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, in hdmi_modb() argument
162 u8 temp = hdmi_readb(hdmi, offset) & ~msk; in hdmi_modb()
165 hdmi_writeb(hdmi, offset, temp); in hdmi_modb()
168 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi) in inno_hdmi_i2c_init() argument
172 ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE; in inno_hdmi_i2c_init()
174 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); in inno_hdmi_i2c_init()
[all …]
|
| D | dw_hdmi-rockchip.c | 74 struct dw_hdmi *hdmi; member
189 static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) in rockchip_hdmi_parse_dt() argument
191 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
193 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
194 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
195 DRM_DEV_ERROR(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
196 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
199 hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
200 if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) { in rockchip_hdmi_parse_dt()
201 hdmi->vpll_clk = NULL; in rockchip_hdmi_parse_dt()
[all …]
|
| /drivers/gpu/drm/zte/ |
| D | zx_hdmi.c | 55 static inline u8 hdmi_readb(struct zx_hdmi *hdmi, u16 offset) in hdmi_readb() argument
57 return readl_relaxed(hdmi->mmio + offset * 4); in hdmi_readb()
60 static inline void hdmi_writeb(struct zx_hdmi *hdmi, u16 offset, u8 val) in hdmi_writeb() argument
62 writel_relaxed(val, hdmi->mmio + offset * 4); in hdmi_writeb()
65 static inline void hdmi_writeb_mask(struct zx_hdmi *hdmi, u16 offset, in hdmi_writeb_mask() argument
70 tmp = hdmi_readb(hdmi, offset); in hdmi_writeb_mask()
72 hdmi_writeb(hdmi, offset, tmp); in hdmi_writeb_mask()
75 static int zx_hdmi_infoframe_trans(struct zx_hdmi *hdmi, in zx_hdmi_infoframe_trans() argument
82 hdmi_writeb(hdmi, TPI_INFO_FSEL, fsel); in zx_hdmi_infoframe_trans()
86 DRM_DEV_ERROR(hdmi->dev, "failed to pack infoframe: %d\n", num); in zx_hdmi_infoframe_trans()
[all …]
|
| /drivers/gpu/drm/mediatek/ |
| D | mtk_hdmi.c | 191 static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) in mtk_hdmi_read() argument
193 return readl(hdmi->regs + offset); in mtk_hdmi_read()
196 static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val) in mtk_hdmi_write() argument
198 writel(val, hdmi->regs + offset); in mtk_hdmi_write()
201 static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) in mtk_hdmi_clear_bits() argument
203 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_clear_bits()
211 static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits) in mtk_hdmi_set_bits() argument
213 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_set_bits()
221 static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask) in mtk_hdmi_mask() argument
223 void __iomem *reg = hdmi->regs + offset; in mtk_hdmi_mask()
[all …]
|
| /drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi4.c | 39 static int hdmi_runtime_get(struct omap_hdmi *hdmi) in hdmi_runtime_get() argument
45 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
47 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
53 static void hdmi_runtime_put(struct omap_hdmi *hdmi) in hdmi_runtime_put() argument
59 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
65 struct omap_hdmi *hdmi = data; in hdmi_irq_handler() local
66 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler()
92 u32 intr4 = hdmi_read_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4); in hdmi_irq_handler()
94 hdmi_write_reg(hdmi->core.base, HDMI_CORE_SYS_INTR4, intr4); in hdmi_irq_handler()
96 hdmi4_cec_irq(&hdmi->core); in hdmi_irq_handler()
[all …]
|
| D | hdmi5.c | 40 static int hdmi_runtime_get(struct omap_hdmi *hdmi) in hdmi_runtime_get() argument
46 r = pm_runtime_get_sync(&hdmi->pdev->dev); in hdmi_runtime_get()
48 pm_runtime_put_noidle(&hdmi->pdev->dev); in hdmi_runtime_get()
54 static void hdmi_runtime_put(struct omap_hdmi *hdmi) in hdmi_runtime_put() argument
60 r = pm_runtime_put_sync(&hdmi->pdev->dev); in hdmi_runtime_put()
66 struct omap_hdmi *hdmi = data; in hdmi_irq_handler() local
67 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler()
90 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
93 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler()
100 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
[all …]
|
| /drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.c | 16 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) in msm_hdmi_set_mode() argument
21 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
24 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
26 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
35 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
36 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
43 struct hdmi *hdmi = dev_id; in msm_hdmi_irq() local
46 msm_hdmi_hpd_irq(hdmi->bridge); in msm_hdmi_irq()
49 msm_hdmi_i2c_irq(hdmi->i2c); in msm_hdmi_irq()
52 if (hdmi->hdcp_ctrl) in msm_hdmi_irq()
[all …]
|
| D | hdmi_hpd.c | 14 static void msm_hdmi_phy_reset(struct hdmi *hdmi) in msm_hdmi_phy_reset() argument
18 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); in msm_hdmi_phy_reset()
22 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
26 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
32 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
36 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
44 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
48 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
54 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
58 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
[all …]
|
| D | hdmi_bridge.c | 24 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on() local
25 const struct hdmi_platform_config *config = hdmi->config; in msm_hdmi_power_on()
28 pm_runtime_get_sync(&hdmi->pdev->dev); in msm_hdmi_power_on()
31 ret = regulator_enable(hdmi->pwr_regs[i]); in msm_hdmi_power_on()
39 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
40 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock); in msm_hdmi_power_on()
48 ret = clk_prepare_enable(hdmi->pwr_clks[i]); in msm_hdmi_power_on()
60 struct hdmi *hdmi = hdmi_bridge->hdmi; in power_off() local
61 const struct hdmi_platform_config *config = hdmi->config; in power_off()
70 clk_disable_unprepare(hdmi->pwr_clks[i]); in power_off()
[all …]
|
| D | hdmi_hdcp.c | 49 struct hdmi *hdmi; member
78 static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, in msm_hdmi_ddc_read() argument
99 rc = i2c_transfer(hdmi->i2c, msgs, 2); in msm_hdmi_ddc_read()
116 static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, in msm_hdmi_ddc_write() argument
141 rc = i2c_transfer(hdmi->i2c, msgs, 1); in msm_hdmi_ddc_write()
159 struct hdmi *hdmi = hdcp_ctrl->hdmi; in msm_hdmi_hdcp_scm_wr() local
167 phy_addr = (u32)hdmi->mmio_phy_addr; in msm_hdmi_hdcp_scm_wr()
190 hdmi_write(hdmi, preg[i], pdata[i]); in msm_hdmi_hdcp_scm_wr()
198 struct hdmi *hdmi = hdcp_ctrl->hdmi; in msm_hdmi_hdcp_irq() local
202 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_hdcp_irq()
[all …]
|
| D | hdmi_i2c.c | 11 struct hdmi *hdmi; member
19 struct hdmi *hdmi = hdmi_i2c->hdmi; in init_ddc() local
21 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, in init_ddc()
23 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, in init_ddc()
26 hdmi_write(hdmi, REG_HDMI_DDC_SPEED, in init_ddc()
30 hdmi_write(hdmi, REG_HDMI_DDC_SETUP, in init_ddc()
34 hdmi_write(hdmi, REG_HDMI_DDC_REF, in init_ddc()
41 struct hdmi *hdmi = hdmi_i2c->hdmi; in ddc_clear_irq() local
42 struct drm_device *dev = hdmi->dev; in ddc_clear_irq()
49 hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL, in ddc_clear_irq()
[all …]
|
| D | hdmi.h | 33 struct hdmi { struct
110 struct hdmi *hdmi; member
115 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
117 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
119 msm_writel(data, hdmi->mmio + reg); in hdmi_write()
122 static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg) in hdmi_read() argument
124 return msm_readl(hdmi->mmio + reg); in hdmi_read()
127 static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg) in hdmi_qfprom_read() argument
129 return msm_readl(hdmi->qfprom_mmio + reg); in hdmi_qfprom_read()
217 int msm_hdmi_audio_update(struct hdmi *hdmi);
[all …]
|
| D | hdmi_audio.c | 74 int msm_hdmi_audio_update(struct hdmi *hdmi) in msm_hdmi_audio_update() argument
76 struct hdmi_audio *audio = &hdmi->audio; in msm_hdmi_audio_update()
87 DBG("video: power_on=%d, pixclock=%lu", hdmi->power_on, hdmi->pixclock); in msm_hdmi_audio_update()
89 if (enabled && !(hdmi->power_on && hdmi->pixclock)) { in msm_hdmi_audio_update()
95 arcs = get_arcs(hdmi->pixclock); in msm_hdmi_audio_update()
98 hdmi->pixclock); in msm_hdmi_audio_update()
104 acr_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_ACR_PKT_CTRL); in msm_hdmi_audio_update()
105 vbi_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_VBI_PKT_CTRL); in msm_hdmi_audio_update()
106 aud_pkt_ctrl = hdmi_read(hdmi, REG_HDMI_AUDIO_PKT_CTRL1); in msm_hdmi_audio_update()
107 infofrm_ctrl = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0); in msm_hdmi_audio_update()
[all …]
|
| /drivers/gpu/drm/sti/ |
| D | sti_hdmi.c | 163 struct sti_hdmi *hdmi; member
176 u32 hdmi_read(struct sti_hdmi *hdmi, int offset) in hdmi_read() argument
178 return readl(hdmi->regs + offset); in hdmi_read()
181 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) in hdmi_write() argument
183 writel(val, hdmi->regs + offset); in hdmi_write()
194 struct sti_hdmi *hdmi = arg; in hdmi_irq_thread() local
197 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) { in hdmi_irq_thread()
198 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; in hdmi_irq_thread()
199 if (hdmi->drm_dev) in hdmi_irq_thread()
200 drm_helper_hpd_irq_event(hdmi->drm_dev); in hdmi_irq_thread()
[all …]
|
| /drivers/gpu/drm/tegra/ |
| D | hdmi.c | 60 struct regulator *hdmi; member
103 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, in tegra_hdmi_readl() argument
106 u32 value = readl(hdmi->regs + (offset << 2)); in tegra_hdmi_readl()
108 trace_hdmi_readl(hdmi->dev, offset, value); in tegra_hdmi_readl()
113 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, in tegra_hdmi_writel() argument
116 trace_hdmi_writel(hdmi->dev, offset, value); in tegra_hdmi_writel()
117 writel(value, hdmi->regs + (offset << 2)); in tegra_hdmi_writel()
412 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) in tegra_hdmi_setup_audio_fs_tables() argument
435 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); in tegra_hdmi_setup_audio_fs_tables()
439 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value) in tegra_hdmi_write_aval() argument
[all …]
|
| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi5.c | 37 static struct omap_hdmi hdmi; variable
45 r = pm_runtime_get_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
47 pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
60 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
89 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
92 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler()
99 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
114 if (hdmi.vdda_reg != NULL) in hdmi_init_regulator()
117 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
123 hdmi.vdda_reg = reg; in hdmi_init_regulator()
[all …]
|
| D | hdmi4.c | 33 static struct omap_hdmi hdmi; variable
41 r = pm_runtime_get_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
43 pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_get()
56 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
95 if (hdmi.vdda_reg != NULL) in hdmi_init_regulator()
98 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
106 hdmi.vdda_reg = reg; in hdmi_init_regulator()
115 r = regulator_enable(hdmi.vdda_reg); in hdmi_power_on_core()
126 hdmi.core_enabled = true; in hdmi_power_on_core()
131 regulator_disable(hdmi.vdda_reg); in hdmi_power_on_core()
[all …]
|
| /drivers/gpu/drm/imx/ |
| D | dw_hdmi-imx.c | 31 struct imx_hdmi *hdmi; member
37 struct dw_hdmi *hdmi; member
43 return container_of(e, struct imx_hdmi_encoder, encoder)->hdmi; in enc_to_imx_hdmi()
112 struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder); in dw_hdmi_imx_encoder_enable() local
113 int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder); in dw_hdmi_imx_encoder_enable()
115 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, in dw_hdmi_imx_encoder_enable()
139 imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in imx6q_hdmi_mode_valid() argument
153 imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in imx6dl_hdmi_mode_valid() argument
204 hdmi_encoder->hdmi = dev_get_drvdata(dev); in dw_hdmi_imx_bind()
213 return drm_bridge_attach(encoder, hdmi_encoder->hdmi->bridge, NULL, 0); in dw_hdmi_imx_bind()
[all …]
|
| /drivers/media/i2c/adv748x/ |
| D | adv748x-hdmi.c | 90 static void adv748x_hdmi_fill_format(struct adv748x_hdmi *hdmi, in adv748x_hdmi_fill_format() argument
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
102 fmt->width = hdmi->timings.bt.width; in adv748x_hdmi_fill_format()
103 fmt->height = hdmi->timings.bt.height; in adv748x_hdmi_fill_format()
220 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); in adv748x_hdmi_s_dv_timings() local
221 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); in adv748x_hdmi_s_dv_timings()
227 if (v4l2_match_dv_timings(&hdmi->timings, timings, 0, false)) in adv748x_hdmi_s_dv_timings()
242 hdmi->timings = *timings; in adv748x_hdmi_s_dv_timings()
260 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); in adv748x_hdmi_g_dv_timings() local
261 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); in adv748x_hdmi_g_dv_timings()
[all …]
|
| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | hdmigv100.c | 33 const u32 hdmi = head * 0x400; in gv100_hdmi_ctrl() local
42 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
43 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
44 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
49 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_hdmi_ctrl()
51 nvkm_wr32(device, 0x6f0008 + hdmi, avi_infoframe.header); in gv100_hdmi_ctrl()
52 nvkm_wr32(device, 0x6f000c + hdmi, avi_infoframe.subpack0_low); in gv100_hdmi_ctrl()
53 nvkm_wr32(device, 0x6f0010 + hdmi, avi_infoframe.subpack0_high); in gv100_hdmi_ctrl()
54 nvkm_wr32(device, 0x6f0014 + hdmi, avi_infoframe.subpack1_low); in gv100_hdmi_ctrl()
55 nvkm_wr32(device, 0x6f0018 + hdmi, avi_infoframe.subpack1_high); in gv100_hdmi_ctrl()
[all …]
|