| /drivers/clk/imx/ |
| D | clk-imx7d.c | 377 static struct clk_hw **hws; variable
385 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx7d_clocks_init()
391 hws = clk_hw_data->hws; in imx7d_clocks_init()
393 hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7d_clocks_init()
394 hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx7d_clocks_init()
395 hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx7d_clocks_init()
402 …hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_s… in imx7d_clocks_init()
403 …hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_… in imx7d_clocks_init()
404 …hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_s… in imx7d_clocks_init()
405 …hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_… in imx7d_clocks_init()
[all …]
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| D | clk-imx8mm.c | 297 static struct clk_hw **hws; variable
306 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx8mm_clocks_probe()
312 hws = clk_hw_data->hws; in imx8mm_clocks_probe()
314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
315 hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mm_clocks_probe()
316 hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mm_clocks_probe()
317 hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mm_clocks_probe()
318 hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mm_clocks_probe()
319 hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mm_clocks_probe()
320 hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mm_clocks_probe()
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| D | clk-imx6sx.c | 85 static struct clk_hw **hws; variable
125 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sx_clocks_init()
131 hws = clk_hw_data->hws; in imx6sx_clocks_init()
133 hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sx_clocks_init()
135 hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6sx_clocks_init()
136 hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6sx_clocks_init()
139 hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
140 hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
143 hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1"); in imx6sx_clocks_init()
144 hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2"); in imx6sx_clocks_init()
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| D | clk-imx8mq.c | 282 static struct clk_hw **hws; variable
291 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL); in imx8mq_clocks_probe()
296 hws = clk_hw_data->hws; in imx8mq_clocks_probe()
298 hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mq_clocks_probe()
299 hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil"); in imx8mq_clocks_probe()
300 hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m"); in imx8mq_clocks_probe()
301 hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m"); in imx8mq_clocks_probe()
302 hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mq_clocks_probe()
303 hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mq_clocks_probe()
304 hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mq_clocks_probe()
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| D | clk-imx6ul.c | 71 static struct clk_hw **hws; variable
119 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6ul_clocks_init()
125 hws = clk_hw_data->hws; in imx6ul_clocks_init()
127 hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6ul_clocks_init()
129 hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6ul_clocks_init()
130 hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6ul_clocks_init()
133 hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6ul_clocks_init()
134 hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6ul_clocks_init()
141 …hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
142 …hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6ul_clocks_init()
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| D | clk-imx8mp.c | 398 static struct clk_hw **hws; variable
419 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CLK_END), GFP_KERNEL); in imx8mp_clocks_probe()
424 hws = clk_hw_data->hws; in imx8mp_clocks_probe()
426 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
427 hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mp_clocks_probe()
428 hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mp_clocks_probe()
429 hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mp_clocks_probe()
430 hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mp_clocks_probe()
431 hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mp_clocks_probe()
432 hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mp_clocks_probe()
[all …]
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| D | clk-imx8mn.c | 293 static struct clk_hw **hws; variable
302 clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, in imx8mn_clocks_probe()
308 hws = clk_hw_data->hws; in imx8mn_clocks_probe()
310 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
311 hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m"); in imx8mn_clocks_probe()
312 hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k"); in imx8mn_clocks_probe()
313 hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); in imx8mn_clocks_probe()
314 hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); in imx8mn_clocks_probe()
315 hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); in imx8mn_clocks_probe()
316 hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); in imx8mn_clocks_probe()
[all …]
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| D | clk-imx6q.c | 92 static struct clk_hw **hws; variable
270 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
271 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in mmdc_ch1_disable()
345 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in init_ldb_clks()
346 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { in init_ldb_clks()
398 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in disable_anatop_clocks()
399 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) in disable_anatop_clocks()
437 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6q_clocks_init()
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
445 hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6q_clocks_init()
[all …]
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| D | clk-imx6sl.c | 100 static struct clk_hw **hws; variable
188 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sl_clocks_init()
194 hws = clk_hw_data->hws; in imx6sl_clocks_init()
196 hws[IMX6SL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sl_clocks_init()
197 hws[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock_hw("ckil", 0); in imx6sl_clocks_init()
198 hws[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock_hw("osc", 0); in imx6sl_clocks_init()
200 hws[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock_hw("anaclk1", 0); in imx6sl_clocks_init()
208 …hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
209 …hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
210 …hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src… in imx6sl_clocks_init()
[all …]
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| D | clk-imx6sll.c | 56 static struct clk_hw **hws; variable
84 clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, in imx6sll_clocks_init()
90 hws = clk_hw_data->hws; in imx6sll_clocks_init()
92 hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx6sll_clocks_init()
94 hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil"); in imx6sll_clocks_init()
95 hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc"); in imx6sll_clocks_init()
98 hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0"); in imx6sll_clocks_init()
99 hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1"); in imx6sll_clocks_init()
115 …hws[IMX6SLL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
116 …hws[IMX6SLL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_sr… in imx6sll_clocks_init()
[all …]
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| D | clk-imx7ulp.c | 49 struct clk_hw **hws; in imx7ulp_clk_scg1_init() local
52 clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END), in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
62 hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc"); in imx7ulp_clk_scg1_init()
63 hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc"); in imx7ulp_clk_scg1_init()
64 hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc"); in imx7ulp_clk_scg1_init()
65 hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc"); in imx7ulp_clk_scg1_init()
66 hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll"); in imx7ulp_clk_scg1_init()
73 …hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_hwseq.c | 32 hws->ctx
34 hws->regs->reg
38 hws->shifts->field_name, hws->masks->field_name
40 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
53 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
80 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
97 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
138 static void dce_disable_sram_shut_down(struct dce_hwseq *hws) in dce_disable_sram_shut_down() argument
[all …]
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| /drivers/clk/x86/ |
| D | clk-fch.c | 34 static struct clk_hw *hws[ST_MAX_CLKS]; variable
45 hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
47 hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", in fch_clk_probe()
50 hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux", in fch_clk_probe()
55 clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk); in fch_clk_probe()
57 hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
61 devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], in fch_clk_probe()
64 hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", in fch_clk_probe()
67 hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", in fch_clk_probe()
71 devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE], in fch_clk_probe()
[all …]
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| /drivers/clk/ |
| D | clk-clps711x.c | 56 clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, in clps711x_clk_init_dt()
108 clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = in clps711x_clk_init_dt()
110 clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = in clps711x_clk_init_dt()
112 clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = in clps711x_clk_init_dt()
114 clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = in clps711x_clk_init_dt()
116 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = in clps711x_clk_init_dt()
118 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = in clps711x_clk_init_dt()
122 clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = in clps711x_clk_init_dt()
126 clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = in clps711x_clk_init_dt()
128 clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = in clps711x_clk_init_dt()
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| D | clk-ast2600.c | 484 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_g6_clk_probe()
495 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; in aspeed_g6_clk_probe()
525 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; in aspeed_g6_clk_probe()
539 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_g6_clk_probe()
553 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; in aspeed_g6_clk_probe()
561 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_g6_clk_probe()
569 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_g6_clk_probe()
583 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; in aspeed_g6_clk_probe()
591 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw; in aspeed_g6_clk_probe()
599 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw; in aspeed_g6_clk_probe()
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| D | clk-aspeed.c | 431 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; in aspeed_clk_probe()
441 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; in aspeed_clk_probe()
455 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; in aspeed_clk_probe()
464 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; in aspeed_clk_probe()
479 aspeed_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw; in aspeed_clk_probe()
487 aspeed_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw; in aspeed_clk_probe()
497 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; in aspeed_clk_probe()
506 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; in aspeed_clk_probe()
513 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; in aspeed_clk_probe()
521 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; in aspeed_clk_probe()
[all …]
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| /drivers/isdn/hardware/mISDN/ |
| D | iohelper.h | 25 #define IOFUNC_IO(name, hws, ap) \ argument
27 struct hws *hw = p; \
31 struct hws *hw = p; \
35 struct hws *hw = p; \
39 struct hws *hw = p; \
43 #define IOFUNC_IND(name, hws, ap) \ argument
45 struct hws *hw = p; \
50 struct hws *hw = p; \
55 struct hws *hw = p; \
60 struct hws *hw = p; \
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| /drivers/gpu/drm/amd/display/dc/dcn303/ |
| D | dcn303_hwseq.c | 18 hws->ctx
20 hws->regs->reg
24 hws->shifts->field_name, hws->masks->field_name
27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn303_dpp_pg_control() argument
32 void dcn303_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn303_hubp_pg_control() argument
37 void dcn303_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn303_dsc_pg_control() argument
42 void dcn303_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) in dcn303_enable_power_gating_plane() argument
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| /drivers/gpu/drm/i915/selftests/ |
| D | igt_spinner.c | 20 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in igt_spinner_init()
21 if (IS_ERR(spin->hws)) { in igt_spinner_init()
22 err = PTR_ERR(spin->hws); in igt_spinner_init()
25 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC); in igt_spinner_init()
36 i915_gem_object_put(spin->hws); in igt_spinner_init()
89 vaddr = igt_spinner_pin_obj(ce, ww, spin->hws, I915_MAP_WB, &spin->hws_vma); in igt_spinner_pin()
115 static u64 hws_address(const struct i915_vma *hws, in hws_address() argument
118 return hws->node.start + seqno_offset(rq->fence.context); in hws_address()
144 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
160 hws = spin->hws_vma; in igt_spinner_create_request()
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| /drivers/clk/bcm/ |
| D | clk-bcm2711-dvp.c | 38 struct_size(dvp->data, hws, NR_CLOCKS), in clk_dvp_probe()
59 data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
65 if (IS_ERR(data->hws[0])) in clk_dvp_probe()
66 return PTR_ERR(data->hws[0]); in clk_dvp_probe()
68 data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev, in clk_dvp_probe()
74 if (IS_ERR(data->hws[1])) { in clk_dvp_probe()
75 ret = PTR_ERR(data->hws[1]); in clk_dvp_probe()
88 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_probe()
91 clk_hw_unregister_gate(data->hws[0]); in clk_dvp_probe()
100 clk_hw_unregister_gate(data->hws[1]); in clk_dvp_remove()
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| /drivers/gpu/drm/amd/display/dc/dcn302/ |
| D | dcn302_hwseq.c | 36 hws->ctx
38 hws->regs->reg
42 hws->shifts->field_name, hws->masks->field_name
45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) in dcn302_dpp_pg_control() argument
50 if (hws->ctx->dc->debug.disable_dpp_power_gate) in dcn302_dpp_pg_control()
102 void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on) in dcn302_hubp_pg_control() argument
107 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn302_hubp_pg_control()
159 void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) in dcn302_dsc_pg_control() argument
165 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn302_dsc_pg_control()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 55 hws->ctx
57 hws->regs->reg
64 hws->shifts->field_name, hws->masks->field_name
69 struct dce_hwseq *hws = dc->hwseq; in dcn31_init_hw() local
95 if (hws->funcs.enable_power_gating_plane) in dcn31_init_hw()
96 hws->funcs.enable_power_gating_plane(hws, true); in dcn31_init_hw()
102 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
103 hws->funcs.disable_vga(dc->hwseq); in dcn31_init_hw()
169 if (hws->funcs.dsc_pg_control != NULL) in dcn31_init_hw()
170 hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false); in dcn31_init_hw()
[all …]
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| /drivers/clk/imgtec/ |
| D | clk-boston.c | 61 onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT), in clk_boston_setup()
73 onecell->hws[BOSTON_CLK_INPUT] = hw; in clk_boston_setup()
80 onecell->hws[BOSTON_CLK_SYS] = hw; in clk_boston_setup()
87 onecell->hws[BOSTON_CLK_CPU] = hw; in clk_boston_setup()
98 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]); in clk_boston_setup()
100 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]); in clk_boston_setup()
102 clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]); in clk_boston_setup()
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| /drivers/clk/xilinx/ |
| D | xlnx_vcu.c | 526 struct clk_hw **hws; in xvcu_register_clock_provider() local
530 data = devm_kzalloc(dev, struct_size(data, hws, CLK_XVCU_NUM_CLOCKS), GFP_KERNEL); in xvcu_register_clock_provider()
534 hws = data->hws; in xvcu_register_clock_provider()
553 hws[CLK_XVCU_ENC_CORE] = in xvcu_register_clock_provider()
558 hws[CLK_XVCU_ENC_MCU] = in xvcu_register_clock_provider()
563 hws[CLK_XVCU_DEC_CORE] = in xvcu_register_clock_provider()
568 hws[CLK_XVCU_DEC_MCU] = in xvcu_register_clock_provider()
580 struct clk_hw **hws = data->hws; in xvcu_unregister_clock_provider() local
582 if (!IS_ERR_OR_NULL(hws[CLK_XVCU_DEC_MCU])) in xvcu_unregister_clock_provider()
583 xvcu_clk_hw_unregister_leaf(hws[CLK_XVCU_DEC_MCU]); in xvcu_unregister_clock_provider()
[all …]
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| /drivers/net/ethernet/chelsio/inline_crypto/chtls/ |
| D | chtls_io.c | 224 struct chtls_hws *hws; in tls_copy_ivs() local
231 hws = &csk->tlshws; in tls_copy_ivs()
252 hws->ivsize = number_of_ivs * CIPHER_BLOCK_SIZE; in tls_copy_ivs()
268 hws->ivsize = 0; in tls_copy_ivs()
282 struct chtls_hws *hws; in tls_copy_tx_key() local
287 hws = &csk->tlshws; in tls_copy_tx_key()
291 kaddr = keyid_to_addr(cdev->kmap.start, hws->txkey); in tls_copy_tx_key()
300 ULPTX_LEN16_V(hws->keylen >> 4)); in tls_copy_tx_key()
305 static u64 tlstx_incr_seqnum(struct chtls_hws *hws) in tlstx_incr_seqnum() argument
307 return hws->tx_seq_no++; in tlstx_incr_seqnum()
[all …]
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