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Searched refs:hwss (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c271 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_attributes()
274 dc->hwss.set_cursor_attribute(pipe_ctx); in program_cursor_attributes()
275 if (dc->hwss.set_cursor_sdr_white_level) in program_cursor_attributes()
276 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in program_cursor_attributes()
280 dc->hwss.cursor_lock(dc, pipe_to_program, false); in program_cursor_attributes()
295 return (dc->hwss.optimize_timing_for_fsft && in dc_optimize_timing_for_fsft()
296 dc->hwss.optimize_timing_for_fsft(dc, &pStream->timing, max_input_rate_in_khz)); in dc_optimize_timing_for_fsft()
375 dc->hwss.cursor_lock(dc, pipe_to_program, true); in program_cursor_position()
378 dc->hwss.set_cursor_position(pipe_ctx); in program_cursor_position()
382 dc->hwss.cursor_lock(dc, pipe_to_program, false); in program_cursor_position()
[all …]
Ddc.c318 dc->hwss.set_drr(&pipe, in dc_stream_adjust_vmin_vmax()
385 dc->hwss.get_position(&pipe, 1, &position); in dc_stream_get_crtc_position()
648 dc->hwss.program_gamut_remap(pipes); in dc_stream_set_gamut_remap()
667 dc->hwss.program_output_csc(dc, in dc_stream_program_csc_matrix()
700 dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, params); in dc_stream_set_static_screen_params()
947 if (dc->hwss.interdependent_update_lock) in apply_ctx_interdependent_lock()
948 dc->hwss.interdependent_update_lock(dc, context, lock); in apply_ctx_interdependent_lock()
958 dc->hwss.pipe_control_lock(dc, pipe_ctx, lock); in apply_ctx_interdependent_lock()
990 if (dc->hwss.apply_ctx_for_surface) { in disable_dangling_plane()
992 dc->hwss.apply_ctx_for_surface(dc, old_stream, 0, dangling_context); in disable_dangling_plane()
[all …]
Ddc_vm_helper.c42 if (dc->hwss.init_sys_ctx) { in dc_setup_system_context()
43 num_vmids = dc->hwss.init_sys_ctx(dc->hwseq, dc, pa_config); in dc_setup_system_context()
60 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid); in dc_setup_vm_context()
Ddc_link_hwss.c88 link->dc->hwss.edp_power_control(link, true); in dp_enable_link_phy()
89 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in dp_enable_link_phy()
222 if (link->dc->hwss.edp_backlight_control) in dp_disable_link_phy()
223 link->dc->hwss.edp_backlight_control(link, false); in dp_disable_link_phy()
225 link->dc->hwss.edp_power_control(link, false); in dp_disable_link_phy()
350 link->dc->hwss.disable_stream(&pipes[i]); in dp_retrain_link_dp_test()
370 link->dc->hwss.enable_stream(&pipes[i]); in dp_retrain_link_dp_test()
372 link->dc->hwss.unblank_stream(&pipes[i], in dp_retrain_link_dp_test()
Ddc_link.c205 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) { in dc_link_wait_for_t12()
206 link->dc->hwss.edp_wait_for_T12(link); in dc_link_wait_for_t12()
234 link->dc->hwss.edp_power_control(link, true); in dc_link_detect_sink()
235 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in dc_link_detect_sink()
1742 link->dc->hwss.edp_power_control(link, true); in enable_link_dp()
1743 link->dc->hwss.edp_wait_for_hpd_ready(link, true); in enable_link_dp()
2653 dc->hwss.set_backlight_level( in dc_link_set_backlight_level()
3288 dc->hwss.update_info_frame(pipe_ctx); in core_link_enable_stream()
3299 dc->hwss.enable_audio_stream(pipe_ctx); in core_link_enable_stream()
3369 dc->hwss.enable_stream(pipe_ctx); in core_link_enable_stream()
[all …]
Ddc_surface.c169 dc->hwss.update_pending_status(pipe_ctx); in dc_plane_get_status()
Ddc_link_dp.c4246 else if (link->dc->hwss.set_disp_pattern_generator) { in set_crtc_test_pattern()
4276 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
4290 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
4314 else if (link->dc->hwss.set_disp_pattern_generator) { in set_crtc_test_pattern()
4327 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
4337 link->dc->hwss.set_disp_pattern_generator(link->dc, in set_crtc_test_pattern()
4396 link->dc->hwss.unblank_stream( in dc_link_dp_set_test_pattern()
4558 link->dc->hwss.update_info_frame(pipe_ctx); in dc_link_dp_set_test_pattern()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_hw_sequencer.c50 dc->hwss.pipe_control_lock = dce_pipe_control_lock; in dce80_hw_sequencer_construct()
51 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce80_hw_sequencer_construct()
52 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce80_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c239 dc->hwss.edp_backlight_control && in dcn31_init_hw()
240 dc->hwss.power_down && in dcn31_init_hw()
241 dc->hwss.edp_power_control) { in dcn31_init_hw()
242 dc->hwss.edp_backlight_control(edp_link, false); in dcn31_init_hw()
243 dc->hwss.power_down(dc); in dcn31_init_hw()
244 dc->hwss.edp_power_control(edp_link, false); in dcn31_init_hw()
255 dc->hwss.power_down) { in dcn31_init_hw()
256 dc->hwss.power_down(dc); in dcn31_init_hw()
515 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn31_reset_back_end_for_pipe()
542 dc->hwss.disable_audio_stream(pipe_ctx); in dcn31_reset_back_end_for_pipe()
Ddcn31_init.c145 dc->hwss = dcn31_funcs; in dcn31_hw_sequencer_construct()
149 dc->hwss.init_hw = dcn20_fpga_init_hw; in dcn31_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c411 dc->hwss.update_plane_addr(dc, pipe_ctx); in dce60_apply_ctx_for_surface()
426 dc->hwss.apply_ctx_for_surface = dce60_apply_ctx_for_surface; in dce60_hw_sequencer_construct()
427 dc->hwss.cursor_lock = dce60_pipe_control_lock; in dce60_hw_sequencer_construct()
428 dc->hwss.pipe_control_lock = dce60_pipe_control_lock; in dce60_hw_sequencer_construct()
429 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce60_hw_sequencer_construct()
430 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce60_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c414 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
422 dc->hwss.update_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
425 dc->hwss.enable_writeback(dc, &wb_info, context); in dcn30_program_all_writeback_pipes_in_tree()
429 dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst); in dcn30_program_all_writeback_pipes_in_tree()
603 dc->hwss.edp_backlight_control && in dcn30_init_hw()
604 dc->hwss.power_down && in dcn30_init_hw()
605 dc->hwss.edp_power_control) { in dcn30_init_hw()
606 dc->hwss.edp_backlight_control(edp_link, false); in dcn30_init_hw()
607 dc->hwss.power_down(dc); in dcn30_init_hw()
608 dc->hwss.edp_power_control(edp_link, false); in dcn30_init_hw()
[all …]
Ddcn30_init.c143 dc->hwss = dcn30_funcs; in dcn30_hw_sequencer_construct()
147 dc->hwss.init_hw = dcn20_fpga_init_hw; in dcn30_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/
Dclk_mgr.c97 if (dc->hwss.exit_optimized_pwr_state) in clk_mgr_exit_optimized_pwr_state()
98 dc->hwss.exit_optimized_pwr_state(dc, dc->current_state); in clk_mgr_exit_optimized_pwr_state()
130 if (dc->hwss.optimize_pwr_state) in clk_mgr_optimize_pwr_state()
131 dc->hwss.optimize_pwr_state(dc, dc->current_state); in clk_mgr_optimize_pwr_state()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c573 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn20_plane_atomic_disable()
581 dc->hwss.set_flip_control_gsl(pipe_ctx, false); in dcn20_plane_atomic_disable()
1017 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn20_blank_pixel_data()
1027 dc->hwss.set_disp_pattern_generator(dc, in dcn20_blank_pixel_data()
1038 dc->hwss.set_disp_pattern_generator(dc, in dcn20_blank_pixel_data()
1052 dc->hwss.set_pipe(pipe_ctx); in dcn20_blank_pixel_data()
1506 dc->hwss.set_cursor_position(pipe_ctx); in dcn20_update_dchubp_dpp()
1507 dc->hwss.set_cursor_attribute(pipe_ctx); in dcn20_update_dchubp_dpp()
1509 if (dc->hwss.set_cursor_sdr_white_level) in dcn20_update_dchubp_dpp()
1510 dc->hwss.set_cursor_sdr_white_level(pipe_ctx); in dcn20_update_dchubp_dpp()
[all …]
Ddcn20_init.c139 dc->hwss = dcn20_funcs; in dcn20_hw_sequencer_construct()
143 dc->hwss.init_hw = dcn20_fpga_init_hw; in dcn20_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_hw_sequencer.c139 dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth; in dce100_hw_sequencer_construct()
140 dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth; in dce100_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c115 dc->hwss.pipe_control_lock(dc, pipe_ctx, true); in dcn10_lock_all_pipes()
117 dc->hwss.pipe_control_lock(dc, pipe_ctx, false); in dcn10_lock_all_pipes()
797 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx); in false_optc_underflow_wa()
950 dc->hwss.disable_audio_stream(pipe_ctx); in dcn10_reset_back_end_for_pipe()
974 dc->hwss.set_abm_immediate_disable(pipe_ctx); in dcn10_reset_back_end_for_pipe()
1182 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); in dcn10_plane_atomic_disable()
1323 dc->hwss.disable_plane(dc, pipe_ctx); in dcn10_init_pipes()
1547 dc->hwss.power_down && in dcn10_power_down_on_boot()
1548 dc->hwss.edp_power_control) { in dcn10_power_down_on_boot()
1550 dc->hwss.power_down(dc); in dcn10_power_down_on_boot()
[all …]
Ddcn10_init.c122 dc->hwss = dcn10_funcs; in dcn10_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_init.c145 dc->hwss = dcn21_funcs; in dcn21_hw_sequencer_construct()
149 dc->hwss.init_hw = dcn20_fpga_init_hw; in dcn21_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_init.c145 dc->hwss = dcn301_funcs; in dcn301_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_hw_sequencer.c269 dc->hwss.update_dchub = dce120_update_dchub; in dce120_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c680 dc->hwss.update_info_frame(pipe_ctx); in dce110_enable_stream()
1175 dc->hwss.disable_audio_stream(pipe_ctx); in dce110_disable_stream()
1212 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); in dce110_blank_stream()
1629 dc->hwss.disable_plane(dc, in disable_vga_and_power_gate_all_controllers()
1754 dc->hwss.edp_power_control(edp_link_with_sink, false); in dce110_enable_accelerated_mode()
2074 dc->hwss.disable_plane(dc, pipe_ctx_old); in dce110_reset_hw_ctx_wrap()
2765 dc->hwss.update_plane_addr(dc, pipe_ctx); in dce110_apply_ctx_for_surface()
3008 dc->hwss = dce110_funcs; in dce110_hw_sequencer_construct()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c3031 if (!dc->hwss.log_hw_state) in dtn_log_read()
3034 dc->hwss.log_hw_state(dc, &log_ctx); in dtn_log_read()
3069 if (dc->hwss.log_hw_state) in dtn_log_write()
3070 dc->hwss.log_hw_state(dc, NULL); in dtn_log_write()
3285 if (!dc->hwss.get_dcc_en_bits) { in dcc_en_bits_read()
3290 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); in dcc_en_bits_read()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c1012 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && in get_pixel_clk_frequency_100hz()
1099 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && in dcn20_program_pix_clk()

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