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Searched refs:ictrl (Results 1 – 7 of 7) sorted by relevance

/drivers/scsi/
Dqla1280.c741 RD_REG_WORD(&reg->ictrl), RD_REG_WORD(&reg->istatus)); in qla1280_mailbox_timeout()
843 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()
1061 WRT_REG_WORD(&ha->iobase->ictrl, 0); in qla1280_disable_intrs()
1062 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()
1069 WRT_REG_WORD(&ha->iobase->ictrl, (ISP_EN_INT | ISP_EN_RISC)); in qla1280_enable_intrs()
1070 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()
1564 WRT_REG_WORD(&reg->ictrl, ISP_RESET); in qla1280_chip_diag()
1574 data = qla1280_debounce_register(&reg->ictrl); in qla1280_chip_diag()
1580 data = RD_REG_WORD(&reg->ictrl); in qla1280_chip_diag()
2686 WRT_REG_WORD(&reg->ictrl, ISP_RESET); in qla1280_reset_adapter()
Dqla1280.h133 uint16_t ictrl; /* Interface control */ member
/drivers/scsi/qla2xxx/
Dqla_dbg.c1132 wrt_reg_dword(&reg->ictrl, 0); in qla24xx_fw_dump()
1133 rd_reg_dword(&reg->ictrl); in qla24xx_fw_dump()
1395 wrt_reg_dword(&reg->ictrl, 0); in qla25xx_fw_dump()
1396 rd_reg_dword(&reg->ictrl); in qla25xx_fw_dump()
1706 wrt_reg_dword(&reg->ictrl, 0); in qla81xx_fw_dump()
1707 rd_reg_dword(&reg->ictrl); in qla81xx_fw_dump()
2041 wrt_reg_dword(&reg->ictrl, 0); in qla83xx_fw_dump()
2042 rd_reg_dword(&reg->ictrl); in qla83xx_fw_dump()
Dqla_mbx.c419 uint32_t ictrl, host_status, hccr; in qla2x00_mailbox_command() local
428 ictrl = rd_reg_dword(&reg->isp24.ictrl); in qla2x00_mailbox_command()
435 command, ictrl, jiffies, mb[0], mb[1], mb[2], mb[3], in qla2x00_mailbox_command()
441 ictrl = rd_reg_word(&reg->isp.ictrl); in qla2x00_mailbox_command()
444 "mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]); in qla2x00_mailbox_command()
452 if (w == 0xffff || ictrl == 0xffffffff || in qla2x00_mailbox_command()
589 rd_reg_dword(&reg->isp24.ictrl), in qla2x00_mailbox_command()
595 rd_reg_word(&reg->isp.ictrl), in qla2x00_mailbox_command()
Dqla_os.c1997 wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC); in qla2x00_enable_intrs()
1998 rd_reg_word(&reg->ictrl); in qla2x00_enable_intrs()
2012 wrt_reg_word(&reg->ictrl, 0); in qla2x00_disable_intrs()
2013 rd_reg_word(&reg->ictrl); in qla2x00_disable_intrs()
2025 wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT); in qla24xx_enable_intrs()
2026 rd_reg_dword(&reg->ictrl); in qla24xx_enable_intrs()
2040 wrt_reg_dword(&reg->ictrl, 0); in qla24xx_disable_intrs()
2041 rd_reg_dword(&reg->ictrl); in qla24xx_disable_intrs()
Dqla_fw.h1198 __le32 ictrl; /* Interrupt control. */ member
Dqla_def.h787 __le16 ictrl; /* Interrupt control */ member