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Searched refs:init_regs (Results 1 – 16 of 16) sorted by relevance

/drivers/mfd/
Datc260x-core.c163 const struct atc260x_init_regs *regs = atc260x->init_regs; in atc260x_cmu_reset()
176 const struct atc260x_init_regs *regs = atc260x->init_regs; in atc260x_dev_init()
217 atc260x->init_regs = &atc2603c_init_regs; in atc260x_match_device()
226 atc260x->init_regs = &atc2609a_init_regs; in atc260x_match_device()
/drivers/clk/meson/
Dmeson-eeclk.h18 const struct reg_sequence *init_regs; member
Dclk-mpll.h21 const struct reg_sequence *init_regs; member
Dclk-pll.h39 const struct reg_sequence *init_regs; member
Dmeson-eeclk.c40 regmap_multi_reg_write(map, data->init_regs, data->init_count); in meson_eeclkc_probe()
Dclk-mpll.c138 regmap_multi_reg_write(clk->map, mpll->init_regs, in mpll_init()
Dclk-pll.c300 regmap_multi_reg_write(clk->map, pll->init_regs, in meson_clk_pll_init()
Dg12a.c1655 .init_regs = g12a_gp0_init_regs,
1795 .init_regs = g12a_hifi_init_regs,
1887 .init_regs = g12a_pcie_pll_init_regs,
2226 .init_regs = g12a_mpll0_init_regs,
2280 .init_regs = g12a_mpll1_init_regs,
2334 .init_regs = g12a_mpll2_init_regs,
2388 .init_regs = g12a_mpll3_init_regs,
5417 .init_regs = g12a_init_regs,
Daxg.c220 .init_regs = axg_gp0_init_regs,
292 .init_regs = axg_hifi_init_regs,
745 .init_regs = axg_pcie_init_regs,
Dgxbb.c463 .init_regs = gxbb_gp0_init_regs,
517 .init_regs = gxl_gp0_init_regs,
Dmeson8b.c1977 .init_regs = meson8m2_gp_pll_init_regs,
/drivers/media/tuners/
Dtda18250.c127 static const u8 init_regs[][2] = { in tda18250_init() local
186 for (i = 0; i < ARRAY_SIZE(init_regs); i++) { in tda18250_init()
187 ret = regmap_write(dev->regmap, init_regs[i][0], in tda18250_init()
188 init_regs[i][1]); in tda18250_init()
Dmxl5007t.c515 struct reg_pair_t *init_regs; in mxl5007t_tuner_init() local
519 init_regs = mxl5007t_calc_init_regs(state, mode); in mxl5007t_tuner_init()
521 ret = mxl5007t_write_regs(state, init_regs); in mxl5007t_tuner_init()
/drivers/media/i2c/
Dimx274.c176 const struct reg_8 *init_regs; member
496 .init_regs = imx274_mode1_3840x2160_raw10,
506 .init_regs = imx274_mode3_1920x1080_raw10,
516 .init_regs = imx274_mode5_1280x720_raw10,
526 .init_regs = imx274_mode6_1280x540_raw10,
777 err = imx274_write_table(priv, priv->mode->init_regs); in imx274_mode_regs()
Dmt9m001.c170 static const struct mt9m001_reg init_regs[] = { in mt9m001_init() local
183 return multi_reg_write(client, init_regs, ARRAY_SIZE(init_regs)); in mt9m001_init()
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_2.c350 const struct soc15_reg_entry *init_regs, u32 regs_size, in gfx_v9_4_2_run_shader() argument
382 ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) in gfx_v9_4_2_run_shader()
384 ib->ptr[ib->length_dw++] = init_regs[i].reg_value; in gfx_v9_4_2_run_shader()