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Searched refs:initial_offset (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/
Ddrm_dsc.c203 pps_payload->initial_offset = in drm_dsc_pps_payload_pack()
204 cpu_to_be16(dsc_cfg->initial_offset); in drm_dsc_pps_payload_pack()
368 vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
397 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + in drm_dsc_compute_rc_parameters()
/drivers/gpu/drm/amd/display/dc/dsc/
Drc_calc_dpi.c52 to->initial_offset = from->initial_offset; in copy_pps_fields()
77 dsc_cfg->initial_offset = rc->initial_fullness_offset; in copy_rc_to_cfg()
/drivers/media/test-drivers/vidtv/
Dvidtv_mux.c158 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_push_si() local
214 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_push_si()
285 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_packetize_access_units() local
318 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_packetize_access_units()
356 u32 initial_offset = m->mux_buf_offset; in vidtv_mux_pad_with_nulls() local
370 nbytes = m->mux_buf_offset - initial_offset; in vidtv_mux_pad_with_nulls()
/drivers/gpu/drm/i915/display/
Dintel_vdsc.c43 u16 initial_offset; member
401 rc->initial_offset = 2048; in calculate_rc_params()
403 rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2); in calculate_rc_params()
405 rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2); in calculate_rc_params()
407 rc->initial_offset = 6144; in calculate_rc_params()
510 vdsc_cfg->initial_offset = rc_params->initial_offset; in intel_dsc_compute_params()
542 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset); in intel_dsc_compute_params()
803 DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); in intel_dsc_pps_configure()
/drivers/nvdimm/
Dbtt_devs.c276 nd_btt->initial_offset = 0; in nd_btt_version()
291 nd_btt->initial_offset = SZ_4K; in nd_btt_version()
Dbtt.c35 return offset + nd_btt->initial_offset; in adjust_initial_offset()
1687 rawsize = size - nd_btt->initial_offset; in nvdimm_namespace_attach_btt()
1691 ARENA_MIN_SIZE + nd_btt->initial_offset); in nvdimm_namespace_attach_btt()
Dnd.h340 int initial_offset; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c306 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); in dsc_log_pps()
513 reg_vals->pps.initial_offset = 6144; in dsc_init_reg_values()
629 INITIAL_OFFSET, reg_vals->pps.initial_offset, in dsc_write_to_registers()
/drivers/gpu/drm/i915/
Di915_reg.h12547 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) argument