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Searched refs:intf_cfg (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_ctl.c518 u32 intf_cfg = 0; in dpu_hw_ctl_intf_cfg() local
520 intf_cfg |= (cfg->intf & 0xF) << 4; in dpu_hw_ctl_intf_cfg()
523 intf_cfg |= BIT(19); in dpu_hw_ctl_intf_cfg()
524 intf_cfg |= (cfg->mode_3d - 0x1) << 20; in dpu_hw_ctl_intf_cfg()
529 intf_cfg &= ~BIT(17); in dpu_hw_ctl_intf_cfg()
530 intf_cfg &= ~(0x3 << 15); in dpu_hw_ctl_intf_cfg()
533 intf_cfg |= BIT(17); in dpu_hw_ctl_intf_cfg()
534 intf_cfg |= ((cfg->stream_sel & 0x3) << 15); in dpu_hw_ctl_intf_cfg()
541 DPU_REG_WRITE(c, CTL_TOP, intf_cfg); in dpu_hw_ctl_intf_cfg()
Ddpu_hw_intf.c94 u32 intf_cfg, intf_cfg2 = 0, display_data_hctl = 0; in dpu_hw_intf_setup_timing_engine() local
97 intf_cfg = DPU_REG_READ(c, INTF_CONFIG); in dpu_hw_intf_setup_timing_engine()
129 intf_cfg |= BIT(29); /* ACTIVE_H_ENABLE */ in dpu_hw_intf_setup_timing_engine()
135 intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */ in dpu_hw_intf_setup_timing_engine()
202 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
Ddpu_encoder_phys_vid.c249 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in dpu_encoder_phys_vid_setup_timing_engine() local
283 intf_cfg.intf = phys_enc->hw_intf->idx; in dpu_encoder_phys_vid_setup_timing_engine()
284 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; in dpu_encoder_phys_vid_setup_timing_engine()
285 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ in dpu_encoder_phys_vid_setup_timing_engine()
286 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in dpu_encoder_phys_vid_setup_timing_engine()
288 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
293 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); in dpu_encoder_phys_vid_setup_timing_engine()
303 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
Ddpu_encoder_phys_cmd.c63 struct dpu_hw_intf_cfg intf_cfg = { 0 }; in _dpu_encoder_phys_cmd_update_intf_cfg() local
69 intf_cfg.intf = phys_enc->intf_idx; in _dpu_encoder_phys_cmd_update_intf_cfg()
70 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD; in _dpu_encoder_phys_cmd_update_intf_cfg()
71 intf_cfg.stream_sel = cmd_enc->stream_sel; in _dpu_encoder_phys_cmd_update_intf_cfg()
72 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); in _dpu_encoder_phys_cmd_update_intf_cfg()
73 ctl->ops.setup_intf_cfg(ctl, &intf_cfg); in _dpu_encoder_phys_cmd_update_intf_cfg()