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Searched refs:lane_settings (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c382 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); in dpcd_set_lt_pattern_and_lane_settings()
384 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); in dpcd_set_lt_pattern_and_lane_settings()
387 (lt_settings->lane_settings[lane].VOLTAGE_SWING == in dpcd_set_lt_pattern_and_lane_settings()
390 (lt_settings->lane_settings[lane].PRE_EMPHASIS == in dpcd_set_lt_pattern_and_lane_settings()
447 link->cur_lane_setting = lt_settings->lane_settings[0]; in dpcd_set_lt_pattern_and_lane_settings()
496 dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING; in dp_update_drive_settings()
498 dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing; in dp_update_drive_settings()
501 dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS; in dp_update_drive_settings()
503 dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis; in dp_update_drive_settings()
506 dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2; in dp_update_drive_settings()
[all …]
/drivers/gpu/drm/amd/display/include/
Dlink_service_types.h83 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; member
Dbios_parser_types.h161 uint32_t lane_settings; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c1127 link_settings->lane_settings[lane].VOLTAGE_SWING; in dcn10_link_encoder_dp_set_lane_settings()
1129 link_settings->lane_settings[lane].PRE_EMPHASIS; in dcn10_link_encoder_dp_set_lane_settings()
1137 link_settings->lane_settings[lane].POST_CURSOR2; in dcn10_link_encoder_dp_set_lane_settings()
1141 cntl.lane_settings = training_lane_set.raw; in dcn10_link_encoder_dp_set_lane_settings()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c1351 link_settings->lane_settings[lane].VOLTAGE_SWING; in dce110_link_encoder_dp_set_lane_settings()
1353 link_settings->lane_settings[lane].PRE_EMPHASIS; in dce110_link_encoder_dp_set_lane_settings()
1361 link_settings->lane_settings[lane].POST_CURSOR2; in dce110_link_encoder_dp_set_lane_settings()
1365 cntl.lane_settings = training_lane_set.raw; in dce110_link_encoder_dp_set_lane_settings()
/drivers/gpu/drm/amd/display/dc/bios/
Dcommand_table.c473 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v2()
601 params.asMode.ucLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v3()
734 params.asMode.ucLaneSet = (uint8_t)(cntl->lane_settings); in transmitter_control_v4()
831 params.ucDPLaneSet = (uint8_t) cntl->lane_settings; in transmitter_control_v1_5()
881 params.ucDPLaneSet = (uint8_t)cntl->lane_settings; in transmitter_control_v1_6()
Dcommand_table2.c283 ps.param.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; in transmitter_control_v1_6()
347 dig_v1_7.mode_laneset.dplaneset = (uint8_t)cntl->lane_settings; in transmitter_control_v1_7()
/drivers/gpu/drm/amd/display/dc/
Ddc_dp_types.h122 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; member
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c542 link_lane_settings.lane_settings[r].VOLTAGE_SWING = in dp_phy_settings_write()
544 link_lane_settings.lane_settings[r].PRE_EMPHASIS = in dp_phy_settings_write()
546 link_lane_settings.lane_settings[r].POST_CURSOR2 = in dp_phy_settings_write()
740 link_training_settings.lane_settings[i] = link->cur_lane_setting; in dp_phy_test_pattern_debugfs_write()