| /drivers/thunderbolt/ |
| D | dma_test.c | 104 unsigned int link_width; member
393 *val = dt->link_width; in lanes_get()
403 dt->link_width = val; in lanes_set()
466 switch (dt->link_width) { in dma_test_set_bonding()
492 } else if (dt->link_width && in dma_test_check_errors()
493 dt->xd->link_width != dt->link_width) { in dma_test_check_errors()
530 if (dt->link_width) in test_store()
531 dev_dbg(&svc->dev, "link_width: %u\n", dt->link_width); in test_store()
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| D | tb.c | 369 int link_speed, link_width, up_bw, down_bw; in tb_available_bandwidth() local
382 link_width = port->bonded ? 2 : 1; in tb_available_bandwidth()
384 up_bw = link_speed * link_width * 1000; /* Mb/s */ in tb_available_bandwidth()
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| D | xdomain.c | 996 if (xd->link_width != ret) in tb_xdomain_update_link_attributes()
999 xd->link_width = ret; in tb_xdomain_update_link_attributes()
1261 return sprintf(buf, "%u\n", xd->link_width); in lanes_show()
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| D | switch.c | 1712 return sprintf(buf, "%u\n", sw->link_width); in lanes_show()
2516 if (sw->link_width != ret) in tb_switch_update_link_attributes()
2518 sw->link_width = ret; in tb_switch_update_link_attributes()
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| D | tb.h | 171 unsigned int link_width; member
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| D | icm.c | 856 sw->link_width = dual_lane ? 2 : 1; in icm_fr_device_connected()
1279 sw->link_width = dual_lane ? 2 : 1; in __icm_tr_device_connected()
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| /drivers/infiniband/hw/hfi1/ |
| D | mad.h | 400 u16 tx_link_width(u16 link_width);
401 u64 get_xmit_wait_counters(struct hfi1_pportdata *ppd, u16 link_width,
431 static inline u64 convert_xmit_counter(u64 xmit_wait_val, u16 link_width, in convert_xmit_counter() argument
434 return (xmit_wait_val * 2 * (FACTOR_LINK_WIDTH / link_width) in convert_xmit_counter()
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| D | mad.c | 803 pi->link_width.enabled = cpu_to_be16(ppd->link_width_enabled); in __subn_get_opa_portinfo()
804 pi->link_width.supported = cpu_to_be16(ppd->link_width_supported); in __subn_get_opa_portinfo()
805 pi->link_width.active = cpu_to_be16(ppd->link_width_active); in __subn_get_opa_portinfo()
1443 lwe = be16_to_cpu(pi->link_width.enabled); in __subn_set_opa_portinfo()
2617 u16 tx_link_width(u16 link_width) in tx_link_width() argument
2622 while (link_width && n) { in tx_link_width()
2623 if (link_width & (1 << (n - 1))) { in tx_link_width()
2651 u16 link_width, u16 link_speed, int vl) in get_xmit_wait_counters() argument
2676 ppd->prev_link_width = link_width; in get_xmit_wait_counters()
2700 u16 link_width; in pma_get_opa_portstatus() local
[all …]
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| D | hfi.h | 1643 u16 link_width = ppd->link_width_active; in active_egress_rate() local
1651 switch (link_width) { in active_egress_rate()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | nbio_v2_3.c | 484 uint32_t link_width = 0; in nbio_v2_3_apply_lc_spc_mode_wa() local
491 link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in nbio_v2_3_apply_lc_spc_mode_wa()
498 if (0x3 == link_width) { in nbio_v2_3_apply_lc_spc_mode_wa()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | smu_v11_0.h | 66 static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
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| /drivers/ntb/hw/mscc/ |
| D | ntb_hw_switchtec.c | 88 enum ntb_width link_width; member
440 sndev->link_width = NTB_WIDTH_NONE; in switchtec_ntb_set_link_speed()
450 sndev->link_width = min(self_width, peer_width); in switchtec_ntb_set_link_speed()
566 *width = sndev->link_width; in switchtec_ntb_link_is_up()
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| /drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0.c | 75 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
1889 return link_width[width_level]; in smu_v13_0_get_current_pcie_link_width()
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| /drivers/scsi/qla4xxx/ |
| D | ql4_def.h | 740 int link_width; member
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| D | ql4_nx.c | 1762 ha->link_width = (lnk >> 4) & 0x3f; in qla4_82xx_start_firmware()
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| /drivers/net/ethernet/myricom/myri10ge/ |
| D | myri10ge.c | 3192 int link_width; in myri10ge_select_firmware() local
3196 link_width = (lnk >> 4) & 0x3f; in myri10ge_select_firmware()
3201 if (link_width < 8) { in myri10ge_select_firmware()
3203 link_width); in myri10ge_select_firmware()
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| /drivers/rapidio/devices/ |
| D | rio_mport_cdev.c | 2420 md->properties.link_width = attr.link_width; in mport_cdev_add()
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| D | tsi721.c | 2557 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27; in tsi721_query_mport()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 55 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
2220 return link_width[width_level]; in vega12_get_current_pcie_link_width()
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| D | smu7_hwmgr.c | 226 uint32_t link_width; in smu7_get_current_pcie_lane_number() local
229 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()
232 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()
235 return decode_pcie_lane_width(link_width); in smu7_get_current_pcie_lane_number()
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| D | vega20_hwmgr.c | 60 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16}; variable
3330 return link_width[width_level]; in vega20_get_current_pcie_link_width()
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| /drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 4789 u32 link_width = 0; in ci_get_current_pcie_lane_number() local
4791 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()
4792 link_width >>= LC_LINK_WIDTH_RD_SHIFT; in ci_get_current_pcie_lane_number()
4794 switch (link_width) { in ci_get_current_pcie_lane_number()
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | smu_v11_0.c | 2134 return link_width[width_level]; in smu_v11_0_get_current_pcie_link_width()
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | reg.h | 4628 u16 proto_admin, u16 link_width) in mlxsw_reg_ptys_ib_pack() argument
4634 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); in mlxsw_reg_ptys_ib_pack()
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| /drivers/scsi/qla2xxx/ |
| D | qla_nx.c | 2497 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()
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