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Searched refs:m1 (Results 1 – 25 of 66) sorted by relevance

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/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_fw_defs.h17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
35 (IRO[324].base + ((pfId) * IRO[324].m1))
37 (IRO[325].base + ((pfId) * IRO[325].m1))
39 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
[all …]
Dbnx2x_init.h539 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ argument
543 en_mask, {m1, m1h, m2, m3}, #block \
546 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ argument
550 en_mask, {m1, m1h, m2, m3}, #block"_0" \
553 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ argument
557 en_mask, {m1, m1h, m2, m3}, #block"_1" \
/drivers/gpu/drm/i915/display/
Dintel_dpll.c19 } dot, vco, n, m, m1, m2, p, p1; member
31 .m1 = { .min = 18, .max = 26 },
44 .m1 = { .min = 18, .max = 26 },
57 .m1 = { .min = 18, .max = 26 },
70 .m1 = { .min = 8, .max = 18 },
83 .m1 = { .min = 8, .max = 18 },
97 .m1 = { .min = 17, .max = 23 },
112 .m1 = { .min = 16, .max = 23 },
125 .m1 = { .min = 17, .max = 23 },
139 .m1 = { .min = 17, .max = 23 },
[all …]
Dg4x_dp.c30 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
32 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
37 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
39 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
44 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
46 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
60 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
62 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
/drivers/clk/meson/
Dclk-dualdiv.c43 return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2), in __dualdiv_param_to_rate()
44 p->n1 * p->m1 + p->n2 * p->m2); in __dualdiv_param_to_rate()
56 setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1; in meson_clk_dualdiv_recalc_rate()
116 meson_parm_write(clk->map, &dualdiv->m1, setting->m1 - 1); in meson_clk_dualdiv_set_rate()
Dclk-dualdiv.h16 unsigned int m1; member
24 struct parm m1; member
Dg12a-aoclk.c96 .m1 = 8,
131 .m1 = {
222 .m1 = {
/drivers/video/fbdev/intelfb/
Dintelfbhw.c666 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, in calc_vclock() argument
672 m = (5 * (m1 + 2)) + (m2 + 2); in calc_vclock()
716 int i, m1, m2, n, p1, p2; in intelfbhw_print_hw_state() local
728 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
734 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
736 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
739 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
744 m1, m2, n, p1, p2); in intelfbhw_print_hw_state()
746 calc_vclock(index, m1, m2, n, p1, p2, 0)); in intelfbhw_print_hw_state()
756 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; in intelfbhw_print_hw_state()
[all …]
/drivers/net/ethernet/netronome/nfp/flower/
Dconntrack.h18 char *k1, *m1, *k2, *m2; \
21 m1 = (char *)_match1.mask; \
25 if ((k1[i] & m1[i] & m2[i]) ^ \
26 (k2[i] & m1[i] & m2[i])) { \
/drivers/gpu/drm/gma500/
Dgma_display.c729 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in gma_find_best_pll()
785 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
Dcdv_intel_display.c40 .m1 = {.min = 0, .max = 0},
52 .m1 = {.min = 0, .max = 0},
67 .m1 = {.min = 0, .max = 0},
79 .m1 = {.min = 0, .max = 0},
91 .m1 = {.min = 0, .max = 0},
103 .m1 = {.min = 0, .max = 0},
416 clock.m1 = 0; in cdv_intel_find_dp_pll()
422 clock.m1 = 0; in cdv_intel_find_dp_pll()
432 clock.m1 = 0; in cdv_intel_find_dp_pll()
438 clock.m1 = 0; in cdv_intel_find_dp_pll()
[all …]
Dgma_display.h22 int m1, m2; member
41 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
Dpsb_intel_display.c30 .m1 = {.min = 8, .max = 18},
42 .m1 = {.min = 8, .max = 18},
68 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
150 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
330 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in psb_intel_crtc_clock_get()
/drivers/gpu/drm/nouveau/dispnv04/
Darb.c58 int found, mclk_extra, mclk_loop, cbs, m1, p1; in nv04_calc_arb() local
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
93 p1 = m1 * pclk_freq / mclk_freq; in nv04_calc_arb()
95 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
/drivers/firmware/efi/
Dfake_mem.c27 const struct efi_mem_range *m1 = x1; in cmp_fake_mem() local
30 if (m1->range.start < m2->range.start) in cmp_fake_mem()
32 if (m1->range.start > m2->range.start) in cmp_fake_mem()
/drivers/ssb/
Dmain.c846 u32 n1, n2, clock, m1, m2, m3, mc; in ssb_calc_clock_rate() local
886 m1 = (m & SSB_CHIPCO_CLK_M1); in ssb_calc_clock_rate()
896 m1 = clkfactor_f6_resolve(m1); in ssb_calc_clock_rate()
908 return (clock / m1); in ssb_calc_clock_rate()
910 return (clock / (m1 * m2)); in ssb_calc_clock_rate()
912 return (clock / (m1 * m2 * m3)); in ssb_calc_clock_rate()
914 return (clock / (m1 * m3)); in ssb_calc_clock_rate()
918 m1 += SSB_CHIPCO_CLK_T2_BIAS; in ssb_calc_clock_rate()
921 WARN_ON(!((m1 >= 2) && (m1 <= 7))); in ssb_calc_clock_rate()
926 clock /= m1; in ssb_calc_clock_rate()
/drivers/net/ethernet/apm/xgene-v2/
Dmain.c96 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
97 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
98 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_refill_buffers()
203 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
204 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
205 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_start_xmit()
/drivers/net/wireless/intel/iwlegacy/
D4965.c672 const struct il_eeprom_calib_measure *m1; in il4965_interpolate_chan() local
693 m1 = &(il->calib_info->band_info[s].ch1. in il4965_interpolate_chan()
701 m1->actual_pow, ch_i2, in il4965_interpolate_chan()
705 m1->gain_idx, ch_i2, in il4965_interpolate_chan()
709 m1->temperature, in il4965_interpolate_chan()
714 m1->pa_det, ch_i2, in il4965_interpolate_chan()
718 m, m1->actual_pow, m2->actual_pow, in il4965_interpolate_chan()
721 m, m1->gain_idx, m2->gain_idx, in il4965_interpolate_chan()
724 m, m1->pa_det, m2->pa_det, omeas->pa_det); in il4965_interpolate_chan()
726 m, m1->temperature, m2->temperature, in il4965_interpolate_chan()
/drivers/media/cec/platform/meson/
Dao-cec-g12a.c238 unsigned long n2, m1, m2, f1, f2, p1, p2; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate() local
243 m1 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
249 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
250 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
/drivers/net/ethernet/qlogic/qed/
Dqed_hsi.h3006 u16 m1; member
4115 (IRO[1].base + ((port_id) * IRO[1].m1))
4120 (IRO[2].base + ((port_id) * IRO[2].m1))
4125 (IRO[3].base + ((vf_id) * IRO[3].m1))
4130 (IRO[4].base + ((pf_id) * IRO[4].m1))
4135 (IRO[5].base + ((pf_id) * IRO[5].m1))
4140 (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4145 (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4150 (IRO[8].base + ((pq_id) * IRO[8].m1))
4203 (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
[all …]
/drivers/usb/mon/
Dmon_main.c45 struct mon_bus *m1; in mon_reader_add() local
46 m1 = list_entry(p, struct mon_bus, bus_link); in mon_reader_add()
47 m1->u_bus->monitored = 1; in mon_reader_add()
/drivers/i2c/busses/
Di2c-sh7760.c395 unsigned long mck, m1, dff, odff, iclk; in calc_CCR() local
408 scgdm = cdfm = m1 = 0; in calc_CCR()
415 m1 = iclk / (20 + (scgd << 3)); in calc_CCR()
416 dff = abs(scl_hz - m1); in calc_CCR()
/drivers/pwm/
Dpwm-fsl-ftm.c163 enum fsl_pwm_clk m0, m1; in fsl_pwm_calculate_period() local
177 m1 = FSL_PWM_CLK_EXT; in fsl_pwm_calculate_period()
180 m1 = FSL_PWM_CLK_FIX; in fsl_pwm_calculate_period()
187 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); in fsl_pwm_calculate_period()
/drivers/media/common/saa7146/
Dsaa7146_video.c214 int i,p,m1,m2,m3,o1,o2; in saa7146_pgtable_build() local
219 m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
225 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
230 m1 = ((size+PAGE_SIZE)/PAGE_SIZE)-1; in saa7146_pgtable_build()
236 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
268 for(i = m1; i <= m2 ; i++, ptr2++) { in saa7146_pgtable_build()
285 ptr1 = pt1->cpu+m1; in saa7146_pgtable_build()
286 fill = pt1->cpu[m1]; in saa7146_pgtable_build()
287 for(i=m1;i<1024;i++,ptr1++) { in saa7146_pgtable_build()
/drivers/media/pci/ttpci/
Dbudget-av.c462 u8 m1; in philips_su1278_ty_ci_set_symbol_rate() local
474 m1 = 0x14; in philips_su1278_ty_ci_set_symbol_rate()
476 m1 = 0x10; in philips_su1278_ty_ci_set_symbol_rate()
483 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_su1278_ty_ci_set_symbol_rate()
835 u8 m1; in philips_sd1878_ci_set_symbol_rate() local
847 m1 = 0x14; in philips_sd1878_ci_set_symbol_rate()
849 m1 = 0x10; in philips_sd1878_ci_set_symbol_rate()
860 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_sd1878_ci_set_symbol_rate()

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