1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42
43 #include "atomfirmware.h"
44
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46
47 /* Firmware versioning. */
48 #ifdef DMUB_EXPOSE_VERSION
49 #define DMUB_FW_VERSION_GIT_HASH 0x7383caadc
50 #define DMUB_FW_VERSION_MAJOR 0
51 #define DMUB_FW_VERSION_MINOR 0
52 #define DMUB_FW_VERSION_REVISION 79
53 #define DMUB_FW_VERSION_TEST 0
54 #define DMUB_FW_VERSION_VBIOS 0
55 #define DMUB_FW_VERSION_HOTFIX 0
56 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
57 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
58 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
59 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
60 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
61 (DMUB_FW_VERSION_HOTFIX & 0x3F))
62
63 #endif
64
65 //<DMUB_TYPES>==================================================================
66 /* Basic type definitions. */
67
68 #define __forceinline inline
69
70 /**
71 * Flag from driver to indicate that ABM should be disabled gradually
72 * by slowly reversing all backlight programming and pixel compensation.
73 */
74 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
75
76 /**
77 * Flag from driver to indicate that ABM should be disabled immediately
78 * and undo all backlight programming and pixel compensation.
79 */
80 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
81
82 /**
83 * Flag from driver to indicate that ABM should be disabled immediately
84 * and keep the current backlight programming and pixel compensation.
85 */
86 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
87
88 /**
89 * Flag from driver to set the current ABM pipe index or ABM operating level.
90 */
91 #define SET_ABM_PIPE_NORMAL 1
92
93 /**
94 * Number of ambient light levels in ABM algorithm.
95 */
96 #define NUM_AMBI_LEVEL 5
97
98 /**
99 * Number of operating/aggression levels in ABM algorithm.
100 */
101 #define NUM_AGGR_LEVEL 4
102
103 /**
104 * Number of segments in the gamma curve.
105 */
106 #define NUM_POWER_FN_SEGS 8
107
108 /**
109 * Number of segments in the backlight curve.
110 */
111 #define NUM_BL_CURVE_SEGS 16
112
113 /* Maximum number of streams on any ASIC. */
114 #define DMUB_MAX_STREAMS 6
115
116 /* Maximum number of planes on any ASIC. */
117 #define DMUB_MAX_PLANES 6
118
119 /* Trace buffer offset for entry */
120 #define TRACE_BUFFER_ENTRY_OFFSET 16
121
122 /**
123 *
124 * PSR control version legacy
125 */
126 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
127 /**
128 * PSR control version with multi edp support
129 */
130 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
131
132
133 /**
134 * ABM control version legacy
135 */
136 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
137
138 /**
139 * ABM control version with multi edp support
140 */
141 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
142
143 /**
144 * Physical framebuffer address location, 64-bit.
145 */
146 #ifndef PHYSICAL_ADDRESS_LOC
147 #define PHYSICAL_ADDRESS_LOC union large_integer
148 #endif
149
150 /**
151 * OS/FW agnostic memcpy
152 */
153 #ifndef dmub_memcpy
154 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
155 #endif
156
157 /**
158 * OS/FW agnostic memset
159 */
160 #ifndef dmub_memset
161 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
162 #endif
163
164 #if defined(__cplusplus)
165 extern "C" {
166 #endif
167
168 /**
169 * OS/FW agnostic udelay
170 */
171 #ifndef dmub_udelay
172 #define dmub_udelay(microseconds) udelay(microseconds)
173 #endif
174
175 /**
176 * Number of nanoseconds per DMUB tick.
177 * DMCUB_TIMER_CURRENT increments in DMUB ticks, which are 10ns by default.
178 * If DMCUB_TIMER_WINDOW is non-zero this will no longer be true.
179 */
180 #define NS_PER_DMUB_TICK 10
181
182 /**
183 * union dmub_addr - DMUB physical/virtual 64-bit address.
184 */
185 union dmub_addr {
186 struct {
187 uint32_t low_part; /**< Lower 32 bits */
188 uint32_t high_part; /**< Upper 32 bits */
189 } u; /*<< Low/high bit access */
190 uint64_t quad_part; /*<< 64 bit address */
191 };
192
193 /**
194 * Flags that can be set by driver to change some PSR behaviour.
195 */
196 union dmub_psr_debug_flags {
197 /**
198 * Debug flags.
199 */
200 struct {
201 /**
202 * Enable visual confirm in FW.
203 */
204 uint32_t visual_confirm : 1;
205 /**
206 * Use HW Lock Mgr object to do HW locking in FW.
207 */
208 uint32_t use_hw_lock_mgr : 1;
209
210 /**
211 * Unused.
212 * TODO: Remove.
213 */
214 uint32_t log_line_nums : 1;
215 } bitfields;
216
217 /**
218 * Union for debug flags.
219 */
220 uint32_t u32All;
221 };
222
223 /**
224 * DMUB feature capabilities.
225 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
226 */
227 struct dmub_feature_caps {
228 /**
229 * Max PSR version supported by FW.
230 */
231 uint8_t psr;
232 uint8_t reserved[7];
233 };
234
235 #if defined(__cplusplus)
236 }
237 #endif
238
239 //==============================================================================
240 //</DMUB_TYPES>=================================================================
241 //==============================================================================
242 //< DMUB_META>==================================================================
243 //==============================================================================
244 #pragma pack(push, 1)
245
246 /* Magic value for identifying dmub_fw_meta_info */
247 #define DMUB_FW_META_MAGIC 0x444D5542
248
249 /* Offset from the end of the file to the dmub_fw_meta_info */
250 #define DMUB_FW_META_OFFSET 0x24
251
252 /**
253 * struct dmub_fw_meta_info - metadata associated with fw binary
254 *
255 * NOTE: This should be considered a stable API. Fields should
256 * not be repurposed or reordered. New fields should be
257 * added instead to extend the structure.
258 *
259 * @magic_value: magic value identifying DMUB firmware meta info
260 * @fw_region_size: size of the firmware state region
261 * @trace_buffer_size: size of the tracebuffer region
262 * @fw_version: the firmware version information
263 * @dal_fw: 1 if the firmware is DAL
264 */
265 struct dmub_fw_meta_info {
266 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
267 uint32_t fw_region_size; /**< size of the firmware state region */
268 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
269 uint32_t fw_version; /**< the firmware version information */
270 uint8_t dal_fw; /**< 1 if the firmware is DAL */
271 uint8_t reserved[3]; /**< padding bits */
272 };
273
274 /**
275 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
276 */
277 union dmub_fw_meta {
278 struct dmub_fw_meta_info info; /**< metadata info */
279 uint8_t reserved[64]; /**< padding bits */
280 };
281
282 #pragma pack(pop)
283
284 //==============================================================================
285 //< DMUB Trace Buffer>================================================================
286 //==============================================================================
287 /**
288 * dmub_trace_code_t - firmware trace code, 32-bits
289 */
290 typedef uint32_t dmub_trace_code_t;
291
292 /**
293 * struct dmcub_trace_buf_entry - Firmware trace entry
294 */
295 struct dmcub_trace_buf_entry {
296 dmub_trace_code_t trace_code; /**< trace code for the event */
297 uint32_t tick_count; /**< the tick count at time of trace */
298 uint32_t param0; /**< trace defined parameter 0 */
299 uint32_t param1; /**< trace defined parameter 1 */
300 };
301
302 //==============================================================================
303 //< DMUB_STATUS>================================================================
304 //==============================================================================
305
306 /**
307 * DMCUB scratch registers can be used to determine firmware status.
308 * Current scratch register usage is as follows:
309 *
310 * SCRATCH0: FW Boot Status register
311 * SCRATCH5: LVTMA Status Register
312 * SCRATCH15: FW Boot Options register
313 */
314
315 /**
316 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
317 */
318 union dmub_fw_boot_status {
319 struct {
320 uint32_t dal_fw : 1; /**< 1 if DAL FW */
321 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
322 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
323 uint32_t restore_required : 1; /**< 1 if driver should call restore */
324 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
325 uint32_t reserved : 1;
326 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
327
328 } bits; /**< status bits */
329 uint32_t all; /**< 32-bit access to status bits */
330 };
331
332 /**
333 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
334 */
335 enum dmub_fw_boot_status_bit {
336 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
337 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
338 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
339 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
340 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
341 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
342 };
343
344 /* Register bit definition for SCRATCH5 */
345 union dmub_lvtma_status {
346 struct {
347 uint32_t psp_ok : 1;
348 uint32_t edp_on : 1;
349 uint32_t reserved : 30;
350 } bits;
351 uint32_t all;
352 };
353
354 enum dmub_lvtma_status_bit {
355 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
356 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
357 };
358
359 /**
360 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
361 */
362 union dmub_fw_boot_options {
363 struct {
364 uint32_t pemu_env : 1; /**< 1 if PEMU */
365 uint32_t fpga_env : 1; /**< 1 if FPGA */
366 uint32_t optimized_init : 1; /**< 1 if optimized init */
367 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
368 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
369 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
370 uint32_t z10_disable: 1; /**< 1 to disable z10 */
371 uint32_t reserved2: 1; /**< reserved for an unreleased feature */
372 uint32_t reserved_unreleased1: 1; /**< reserved for an unreleased feature */
373 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
374 uint32_t reserved : 23; /**< reserved */
375 } bits; /**< boot bits */
376 uint32_t all; /**< 32-bit access to bits */
377 };
378
379 enum dmub_fw_boot_options_bit {
380 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
381 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
382 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
383 };
384
385 //==============================================================================
386 //</DMUB_STATUS>================================================================
387 //==============================================================================
388 //< DMUB_VBIOS>=================================================================
389 //==============================================================================
390
391 /*
392 * enum dmub_cmd_vbios_type - VBIOS commands.
393 *
394 * Command IDs should be treated as stable ABI.
395 * Do not reuse or modify IDs.
396 */
397 enum dmub_cmd_vbios_type {
398 /**
399 * Configures the DIG encoder.
400 */
401 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
402 /**
403 * Controls the PHY.
404 */
405 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
406 /**
407 * Sets the pixel clock/symbol clock.
408 */
409 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
410 /**
411 * Enables or disables power gating.
412 */
413 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
414 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
415 };
416
417 //==============================================================================
418 //</DMUB_VBIOS>=================================================================
419 //==============================================================================
420 //< DMUB_GPINT>=================================================================
421 //==============================================================================
422
423 /**
424 * The shifts and masks below may alternatively be used to format and read
425 * the command register bits.
426 */
427
428 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
429 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
430
431 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
432 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
433
434 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
435 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
436
437 /**
438 * Command responses.
439 */
440
441 /**
442 * Return response for DMUB_GPINT__STOP_FW command.
443 */
444 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
445
446 /**
447 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
448 */
449 union dmub_gpint_data_register {
450 struct {
451 uint32_t param : 16; /**< 16-bit parameter */
452 uint32_t command_code : 12; /**< GPINT command */
453 uint32_t status : 4; /**< Command status bit */
454 } bits; /**< GPINT bit access */
455 uint32_t all; /**< GPINT 32-bit access */
456 };
457
458 /*
459 * enum dmub_gpint_command - GPINT command to DMCUB FW
460 *
461 * Command IDs should be treated as stable ABI.
462 * Do not reuse or modify IDs.
463 */
464 enum dmub_gpint_command {
465 /**
466 * Invalid command, ignored.
467 */
468 DMUB_GPINT__INVALID_COMMAND = 0,
469 /**
470 * DESC: Queries the firmware version.
471 * RETURN: Firmware version.
472 */
473 DMUB_GPINT__GET_FW_VERSION = 1,
474 /**
475 * DESC: Halts the firmware.
476 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
477 */
478 DMUB_GPINT__STOP_FW = 2,
479 /**
480 * DESC: Get PSR state from FW.
481 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
482 */
483 DMUB_GPINT__GET_PSR_STATE = 7,
484 /**
485 * DESC: Notifies DMCUB of the currently active streams.
486 * ARGS: Stream mask, 1 bit per active stream index.
487 */
488 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
489 /**
490 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
491 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
492 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
493 * RETURN: PSR residency in milli-percent.
494 */
495 DMUB_GPINT__PSR_RESIDENCY = 9,
496
497 /**
498 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
499 */
500 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
501 };
502
503 /**
504 * INBOX0 generic command definition
505 */
506 union dmub_inbox0_cmd_common {
507 struct {
508 uint32_t command_code: 8; /**< INBOX0 command code */
509 uint32_t param: 24; /**< 24-bit parameter */
510 } bits;
511 uint32_t all;
512 };
513
514 /**
515 * INBOX0 hw_lock command definition
516 */
517 union dmub_inbox0_cmd_lock_hw {
518 struct {
519 uint32_t command_code: 8;
520
521 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
522 uint32_t hw_lock_client: 1;
523
524 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
525 uint32_t otg_inst: 3;
526 uint32_t opp_inst: 3;
527 uint32_t dig_inst: 3;
528
529 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
530 uint32_t lock_pipe: 1;
531 uint32_t lock_cursor: 1;
532 uint32_t lock_dig: 1;
533 uint32_t triple_buffer_lock: 1;
534
535 uint32_t lock: 1; /**< Lock */
536 uint32_t should_release: 1; /**< Release */
537 uint32_t reserved: 8; /**< Reserved for extending more clients, HW, etc. */
538 } bits;
539 uint32_t all;
540 };
541
542 union dmub_inbox0_data_register {
543 union dmub_inbox0_cmd_common inbox0_cmd_common;
544 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
545 };
546
547 enum dmub_inbox0_command {
548 /**
549 * DESC: Invalid command, ignored.
550 */
551 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
552 /**
553 * DESC: Notification to acquire/release HW lock
554 * ARGS:
555 */
556 DMUB_INBOX0_CMD__HW_LOCK = 1,
557 };
558 //==============================================================================
559 //</DMUB_GPINT>=================================================================
560 //==============================================================================
561 //< DMUB_CMD>===================================================================
562 //==============================================================================
563
564 /**
565 * Size in bytes of each DMUB command.
566 */
567 #define DMUB_RB_CMD_SIZE 64
568
569 /**
570 * Maximum number of items in the DMUB ringbuffer.
571 */
572 #define DMUB_RB_MAX_ENTRY 128
573
574 /**
575 * Ringbuffer size in bytes.
576 */
577 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
578
579 /**
580 * REG_SET mask for reg offload.
581 */
582 #define REG_SET_MASK 0xFFFF
583
584 /*
585 * enum dmub_cmd_type - DMUB inbox command.
586 *
587 * Command IDs should be treated as stable ABI.
588 * Do not reuse or modify IDs.
589 */
590 enum dmub_cmd_type {
591 /**
592 * Invalid command.
593 */
594 DMUB_CMD__NULL = 0,
595 /**
596 * Read modify write register sequence offload.
597 */
598 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
599 /**
600 * Field update register sequence offload.
601 */
602 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
603 /**
604 * Burst write sequence offload.
605 */
606 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
607 /**
608 * Reg wait sequence offload.
609 */
610 DMUB_CMD__REG_REG_WAIT = 4,
611 /**
612 * Workaround to avoid HUBP underflow during NV12 playback.
613 */
614 DMUB_CMD__PLAT_54186_WA = 5,
615 /**
616 * Command type used to query FW feature caps.
617 */
618 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
619 /**
620 * Command type used for all PSR commands.
621 */
622 DMUB_CMD__PSR = 64,
623 /**
624 * Command type used for all MALL commands.
625 */
626 DMUB_CMD__MALL = 65,
627 /**
628 * Command type used for all ABM commands.
629 */
630 DMUB_CMD__ABM = 66,
631 /**
632 * Command type used for HW locking in FW.
633 */
634 DMUB_CMD__HW_LOCK = 69,
635 /**
636 * Command type used to access DP AUX.
637 */
638 DMUB_CMD__DP_AUX_ACCESS = 70,
639 /**
640 * Command type used for OUTBOX1 notification enable
641 */
642 DMUB_CMD__OUTBOX1_ENABLE = 71,
643 /**
644 * Command type used for all idle optimization commands.
645 */
646 DMUB_CMD__IDLE_OPT = 72,
647 /**
648 * Command type used for all clock manager commands.
649 */
650 DMUB_CMD__CLK_MGR = 73,
651 /**
652 * Command type used for all panel control commands.
653 */
654 DMUB_CMD__PANEL_CNTL = 74,
655 /**
656 * Command type used for EDID CEA parsing
657 */
658 DMUB_CMD__EDID_CEA = 79,
659 /**
660 * Command type used for all VBIOS interface commands.
661 */
662 DMUB_CMD__VBIOS = 128,
663 };
664
665 /**
666 * enum dmub_out_cmd_type - DMUB outbox commands.
667 */
668 enum dmub_out_cmd_type {
669 /**
670 * Invalid outbox command, ignored.
671 */
672 DMUB_OUT_CMD__NULL = 0,
673 /**
674 * Command type used for DP AUX Reply data notification
675 */
676 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
677 };
678
679 #pragma pack(push, 1)
680
681 /**
682 * struct dmub_cmd_header - Common command header fields.
683 */
684 struct dmub_cmd_header {
685 unsigned int type : 8; /**< command type */
686 unsigned int sub_type : 8; /**< command sub type */
687 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
688 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
689 unsigned int reserved0 : 6; /**< reserved bits */
690 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
691 unsigned int reserved1 : 2; /**< reserved bits */
692 };
693
694 /*
695 * struct dmub_cmd_read_modify_write_sequence - Read modify write
696 *
697 * 60 payload bytes can hold up to 5 sets of read modify writes,
698 * each take 3 dwords.
699 *
700 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
701 *
702 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
703 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
704 */
705 struct dmub_cmd_read_modify_write_sequence {
706 uint32_t addr; /**< register address */
707 uint32_t modify_mask; /**< modify mask */
708 uint32_t modify_value; /**< modify value */
709 };
710
711 /**
712 * Maximum number of ops in read modify write sequence.
713 */
714 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
715
716 /**
717 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
718 */
719 struct dmub_rb_cmd_read_modify_write {
720 struct dmub_cmd_header header; /**< command header */
721 /**
722 * Read modify write sequence.
723 */
724 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
725 };
726
727 /*
728 * Update a register with specified masks and values sequeunce
729 *
730 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
731 *
732 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
733 *
734 *
735 * USE CASE:
736 * 1. auto-increment register where additional read would update pointer and produce wrong result
737 * 2. toggle a bit without read in the middle
738 */
739
740 struct dmub_cmd_reg_field_update_sequence {
741 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
742 uint32_t modify_value; /**< value to update with */
743 };
744
745 /**
746 * Maximum number of ops in field update sequence.
747 */
748 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
749
750 /**
751 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
752 */
753 struct dmub_rb_cmd_reg_field_update_sequence {
754 struct dmub_cmd_header header; /**< command header */
755 uint32_t addr; /**< register address */
756 /**
757 * Field update sequence.
758 */
759 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
760 };
761
762
763 /**
764 * Maximum number of burst write values.
765 */
766 #define DMUB_BURST_WRITE_VALUES__MAX 14
767
768 /*
769 * struct dmub_rb_cmd_burst_write - Burst write
770 *
771 * support use case such as writing out LUTs.
772 *
773 * 60 payload bytes can hold up to 14 values to write to given address
774 *
775 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
776 */
777 struct dmub_rb_cmd_burst_write {
778 struct dmub_cmd_header header; /**< command header */
779 uint32_t addr; /**< register start address */
780 /**
781 * Burst write register values.
782 */
783 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
784 };
785
786 /**
787 * struct dmub_rb_cmd_common - Common command header
788 */
789 struct dmub_rb_cmd_common {
790 struct dmub_cmd_header header; /**< command header */
791 /**
792 * Padding to RB_CMD_SIZE
793 */
794 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
795 };
796
797 /**
798 * struct dmub_cmd_reg_wait_data - Register wait data
799 */
800 struct dmub_cmd_reg_wait_data {
801 uint32_t addr; /**< Register address */
802 uint32_t mask; /**< Mask for register bits */
803 uint32_t condition_field_value; /**< Value to wait for */
804 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
805 };
806
807 /**
808 * struct dmub_rb_cmd_reg_wait - Register wait command
809 */
810 struct dmub_rb_cmd_reg_wait {
811 struct dmub_cmd_header header; /**< Command header */
812 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
813 };
814
815 /**
816 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
817 *
818 * Reprograms surface parameters to avoid underflow.
819 */
820 struct dmub_cmd_PLAT_54186_wa {
821 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
822 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
823 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
824 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
825 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
826 struct {
827 uint8_t hubp_inst : 4; /**< HUBP instance */
828 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
829 uint8_t immediate :1; /**< Immediate flip */
830 uint8_t vmid : 4; /**< VMID */
831 uint8_t grph_stereo : 1; /**< 1 if stereo */
832 uint32_t reserved : 21; /**< Reserved */
833 } flip_params; /**< Pageflip parameters */
834 uint32_t reserved[9]; /**< Reserved bits */
835 };
836
837 /**
838 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
839 */
840 struct dmub_rb_cmd_PLAT_54186_wa {
841 struct dmub_cmd_header header; /**< Command header */
842 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
843 };
844
845 /**
846 * struct dmub_rb_cmd_mall - MALL command data.
847 */
848 struct dmub_rb_cmd_mall {
849 struct dmub_cmd_header header; /**< Common command header */
850 union dmub_addr cursor_copy_src; /**< Cursor copy address */
851 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
852 uint32_t tmr_delay; /**< Timer delay */
853 uint32_t tmr_scale; /**< Timer scale */
854 uint16_t cursor_width; /**< Cursor width in pixels */
855 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
856 uint16_t cursor_height; /**< Cursor height in pixels */
857 uint8_t cursor_bpp; /**< Cursor bits per pixel */
858 uint8_t debug_bits; /**< Debug bits */
859
860 uint8_t reserved1; /**< Reserved bits */
861 uint8_t reserved2; /**< Reserved bits */
862 };
863
864 /**
865 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
866 */
867 enum dmub_cmd_idle_opt_type {
868 /**
869 * DCN hardware restore.
870 */
871 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
872
873 /**
874 * DCN hardware save.
875 */
876 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
877 };
878
879 /**
880 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
881 */
882 struct dmub_rb_cmd_idle_opt_dcn_restore {
883 struct dmub_cmd_header header; /**< header */
884 };
885
886 /**
887 * struct dmub_clocks - Clock update notification.
888 */
889 struct dmub_clocks {
890 uint32_t dispclk_khz; /**< dispclk kHz */
891 uint32_t dppclk_khz; /**< dppclk kHz */
892 uint32_t dcfclk_khz; /**< dcfclk kHz */
893 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
894 };
895
896 /**
897 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
898 */
899 enum dmub_cmd_clk_mgr_type {
900 /**
901 * Notify DMCUB of clock update.
902 */
903 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
904 };
905
906 /**
907 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
908 */
909 struct dmub_rb_cmd_clk_mgr_notify_clocks {
910 struct dmub_cmd_header header; /**< header */
911 struct dmub_clocks clocks; /**< clock data */
912 };
913
914 /**
915 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
916 */
917 struct dmub_cmd_digx_encoder_control_data {
918 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
919 };
920
921 /**
922 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
923 */
924 struct dmub_rb_cmd_digx_encoder_control {
925 struct dmub_cmd_header header; /**< header */
926 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
927 };
928
929 /**
930 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
931 */
932 struct dmub_cmd_set_pixel_clock_data {
933 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
934 };
935
936 /**
937 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
938 */
939 struct dmub_rb_cmd_set_pixel_clock {
940 struct dmub_cmd_header header; /**< header */
941 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
942 };
943
944 /**
945 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
946 */
947 struct dmub_cmd_enable_disp_power_gating_data {
948 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
949 };
950
951 /**
952 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
953 */
954 struct dmub_rb_cmd_enable_disp_power_gating {
955 struct dmub_cmd_header header; /**< header */
956 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
957 };
958
959 /**
960 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
961 */
962 struct dmub_dig_transmitter_control_data_v1_7 {
963 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
964 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
965 union {
966 uint8_t digmode; /**< enum atom_encode_mode_def */
967 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
968 } mode_laneset;
969 uint8_t lanenum; /**< Number of lanes */
970 union {
971 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
972 } symclk_units;
973 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
974 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
975 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
976 uint8_t reserved0; /**< For future use */
977 uint8_t reserved1; /**< For future use */
978 uint8_t reserved2[3]; /**< For future use */
979 uint32_t reserved3[11]; /**< For future use */
980 };
981
982 /**
983 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
984 */
985 union dmub_cmd_dig1_transmitter_control_data {
986 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
987 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
988 };
989
990 /**
991 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
992 */
993 struct dmub_rb_cmd_dig1_transmitter_control {
994 struct dmub_cmd_header header; /**< header */
995 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
996 };
997
998 /**
999 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1000 */
1001 struct dmub_rb_cmd_dpphy_init {
1002 struct dmub_cmd_header header; /**< header */
1003 uint8_t reserved[60]; /**< reserved bits */
1004 };
1005
1006 /**
1007 * enum dp_aux_request_action - DP AUX request command listing.
1008 *
1009 * 4 AUX request command bits are shifted to high nibble.
1010 */
1011 enum dp_aux_request_action {
1012 /** I2C-over-AUX write request */
1013 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1014 /** I2C-over-AUX read request */
1015 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1016 /** I2C-over-AUX write status request */
1017 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1018 /** I2C-over-AUX write request with MOT=1 */
1019 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1020 /** I2C-over-AUX read request with MOT=1 */
1021 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1022 /** I2C-over-AUX write status request with MOT=1 */
1023 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1024 /** Native AUX write request */
1025 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1026 /** Native AUX read request */
1027 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1028 };
1029
1030 /**
1031 * enum aux_return_code_type - DP AUX process return code listing.
1032 */
1033 enum aux_return_code_type {
1034 /** AUX process succeeded */
1035 AUX_RET_SUCCESS = 0,
1036 /** AUX process failed with unknown reason */
1037 AUX_RET_ERROR_UNKNOWN,
1038 /** AUX process completed with invalid reply */
1039 AUX_RET_ERROR_INVALID_REPLY,
1040 /** AUX process timed out */
1041 AUX_RET_ERROR_TIMEOUT,
1042 /** HPD was low during AUX process */
1043 AUX_RET_ERROR_HPD_DISCON,
1044 /** Failed to acquire AUX engine */
1045 AUX_RET_ERROR_ENGINE_ACQUIRE,
1046 /** AUX request not supported */
1047 AUX_RET_ERROR_INVALID_OPERATION,
1048 /** AUX process not available */
1049 AUX_RET_ERROR_PROTOCOL_ERROR,
1050 };
1051
1052 /**
1053 * enum aux_channel_type - DP AUX channel type listing.
1054 */
1055 enum aux_channel_type {
1056 /** AUX thru Legacy DP AUX */
1057 AUX_CHANNEL_LEGACY_DDC,
1058 /** AUX thru DPIA DP tunneling */
1059 AUX_CHANNEL_DPIA
1060 };
1061
1062 /**
1063 * struct aux_transaction_parameters - DP AUX request transaction data
1064 */
1065 struct aux_transaction_parameters {
1066 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1067 uint8_t action; /**< enum dp_aux_request_action */
1068 uint8_t length; /**< DP AUX request data length */
1069 uint8_t reserved; /**< For future use */
1070 uint32_t address; /**< DP AUX address */
1071 uint8_t data[16]; /**< DP AUX write data */
1072 };
1073
1074 /**
1075 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1076 */
1077 struct dmub_cmd_dp_aux_control_data {
1078 uint8_t instance; /**< AUX instance or DPIA instance */
1079 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1080 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1081 uint8_t reserved0; /**< For future use */
1082 uint16_t timeout; /**< timeout time in us */
1083 uint16_t reserved1; /**< For future use */
1084 enum aux_channel_type type; /**< enum aux_channel_type */
1085 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1086 };
1087
1088 /**
1089 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1090 */
1091 struct dmub_rb_cmd_dp_aux_access {
1092 /**
1093 * Command header.
1094 */
1095 struct dmub_cmd_header header;
1096 /**
1097 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1098 */
1099 struct dmub_cmd_dp_aux_control_data aux_control;
1100 };
1101
1102 /**
1103 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1104 */
1105 struct dmub_rb_cmd_outbox1_enable {
1106 /**
1107 * Command header.
1108 */
1109 struct dmub_cmd_header header;
1110 /**
1111 * enable: 0x0 -> disable outbox1 notification (default value)
1112 * 0x1 -> enable outbox1 notification
1113 */
1114 uint32_t enable;
1115 };
1116
1117 /* DP AUX Reply command - OutBox Cmd */
1118 /**
1119 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1120 */
1121 struct aux_reply_data {
1122 /**
1123 * Aux cmd
1124 */
1125 uint8_t command;
1126 /**
1127 * Aux reply data length (max: 16 bytes)
1128 */
1129 uint8_t length;
1130 /**
1131 * Alignment only
1132 */
1133 uint8_t pad[2];
1134 /**
1135 * Aux reply data
1136 */
1137 uint8_t data[16];
1138 };
1139
1140 /**
1141 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1142 */
1143 struct aux_reply_control_data {
1144 /**
1145 * Reserved for future use
1146 */
1147 uint32_t handle;
1148 /**
1149 * Aux Instance
1150 */
1151 uint8_t instance;
1152 /**
1153 * Aux transaction result: definition in enum aux_return_code_type
1154 */
1155 uint8_t result;
1156 /**
1157 * Alignment only
1158 */
1159 uint16_t pad;
1160 };
1161
1162 /**
1163 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1164 */
1165 struct dmub_rb_cmd_dp_aux_reply {
1166 /**
1167 * Command header.
1168 */
1169 struct dmub_cmd_header header;
1170 /**
1171 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1172 */
1173 struct aux_reply_control_data control;
1174 /**
1175 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1176 */
1177 struct aux_reply_data reply_data;
1178 };
1179
1180 /* DP HPD Notify command - OutBox Cmd */
1181 /**
1182 * DP HPD Type
1183 */
1184 enum dp_hpd_type {
1185 /**
1186 * Normal DP HPD
1187 */
1188 DP_HPD = 0,
1189 /**
1190 * DP HPD short pulse
1191 */
1192 DP_IRQ
1193 };
1194
1195 /**
1196 * DP HPD Status
1197 */
1198 enum dp_hpd_status {
1199 /**
1200 * DP_HPD status low
1201 */
1202 DP_HPD_UNPLUG = 0,
1203 /**
1204 * DP_HPD status high
1205 */
1206 DP_HPD_PLUG
1207 };
1208
1209 /**
1210 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1211 */
1212 struct dp_hpd_data {
1213 /**
1214 * DP HPD instance
1215 */
1216 uint8_t instance;
1217 /**
1218 * HPD type
1219 */
1220 uint8_t hpd_type;
1221 /**
1222 * HPD status: only for type: DP_HPD to indicate status
1223 */
1224 uint8_t hpd_status;
1225 /**
1226 * Alignment only
1227 */
1228 uint8_t pad;
1229 };
1230
1231 /**
1232 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1233 */
1234 struct dmub_rb_cmd_dp_hpd_notify {
1235 /**
1236 * Command header.
1237 */
1238 struct dmub_cmd_header header;
1239 /**
1240 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1241 */
1242 struct dp_hpd_data hpd_data;
1243 };
1244
1245 /*
1246 * Command IDs should be treated as stable ABI.
1247 * Do not reuse or modify IDs.
1248 */
1249
1250 /**
1251 * PSR command sub-types.
1252 */
1253 enum dmub_cmd_psr_type {
1254 /**
1255 * Set PSR version support.
1256 */
1257 DMUB_CMD__PSR_SET_VERSION = 0,
1258 /**
1259 * Copy driver-calculated parameters to PSR state.
1260 */
1261 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1262 /**
1263 * Enable PSR.
1264 */
1265 DMUB_CMD__PSR_ENABLE = 2,
1266
1267 /**
1268 * Disable PSR.
1269 */
1270 DMUB_CMD__PSR_DISABLE = 3,
1271
1272 /**
1273 * Set PSR level.
1274 * PSR level is a 16-bit value dicated by driver that
1275 * will enable/disable different functionality.
1276 */
1277 DMUB_CMD__PSR_SET_LEVEL = 4,
1278
1279 /**
1280 * Forces PSR enabled until an explicit PSR disable call.
1281 */
1282 DMUB_CMD__PSR_FORCE_STATIC = 5,
1283 };
1284
1285 /**
1286 * PSR versions.
1287 */
1288 enum psr_version {
1289 /**
1290 * PSR version 1.
1291 */
1292 PSR_VERSION_1 = 0,
1293 /**
1294 * PSR not supported.
1295 */
1296 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
1297 };
1298
1299 /**
1300 * enum dmub_cmd_mall_type - MALL commands
1301 */
1302 enum dmub_cmd_mall_type {
1303 /**
1304 * Allows display refresh from MALL.
1305 */
1306 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1307 /**
1308 * Disallows display refresh from MALL.
1309 */
1310 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1311 /**
1312 * Cursor copy for MALL.
1313 */
1314 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1315 /**
1316 * Controls DF requests.
1317 */
1318 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1319 };
1320
1321
1322 /**
1323 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1324 */
1325 struct dmub_cmd_psr_copy_settings_data {
1326 /**
1327 * Flags that can be set by driver to change some PSR behaviour.
1328 */
1329 union dmub_psr_debug_flags debug;
1330 /**
1331 * 16-bit value dicated by driver that will enable/disable different functionality.
1332 */
1333 uint16_t psr_level;
1334 /**
1335 * DPP HW instance.
1336 */
1337 uint8_t dpp_inst;
1338 /**
1339 * MPCC HW instance.
1340 * Not used in dmub fw,
1341 * dmub fw will get active opp by reading odm registers.
1342 */
1343 uint8_t mpcc_inst;
1344 /**
1345 * OPP HW instance.
1346 * Not used in dmub fw,
1347 * dmub fw will get active opp by reading odm registers.
1348 */
1349 uint8_t opp_inst;
1350 /**
1351 * OTG HW instance.
1352 */
1353 uint8_t otg_inst;
1354 /**
1355 * DIG FE HW instance.
1356 */
1357 uint8_t digfe_inst;
1358 /**
1359 * DIG BE HW instance.
1360 */
1361 uint8_t digbe_inst;
1362 /**
1363 * DP PHY HW instance.
1364 */
1365 uint8_t dpphy_inst;
1366 /**
1367 * AUX HW instance.
1368 */
1369 uint8_t aux_inst;
1370 /**
1371 * Determines if SMU optimzations are enabled/disabled.
1372 */
1373 uint8_t smu_optimizations_en;
1374 /**
1375 * Unused.
1376 * TODO: Remove.
1377 */
1378 uint8_t frame_delay;
1379 /**
1380 * If RFB setup time is greater than the total VBLANK time,
1381 * it is not possible for the sink to capture the video frame
1382 * in the same frame the SDP is sent. In this case,
1383 * the frame capture indication bit should be set and an extra
1384 * static frame should be transmitted to the sink.
1385 */
1386 uint8_t frame_cap_ind;
1387 /**
1388 * Explicit padding to 4 byte boundary.
1389 */
1390 uint8_t pad[2];
1391 /**
1392 * Multi-display optimizations are implemented on certain ASICs.
1393 */
1394 uint8_t multi_disp_optimizations_en;
1395 /**
1396 * The last possible line SDP may be transmitted without violating
1397 * the RFB setup time or entering the active video frame.
1398 */
1399 uint16_t init_sdp_deadline;
1400 /**
1401 * Explicit padding to 4 byte boundary.
1402 */
1403 uint16_t pad2;
1404 /**
1405 * Length of each horizontal line in us.
1406 */
1407 uint32_t line_time_in_us;
1408 /**
1409 * FEC enable status in driver
1410 */
1411 uint8_t fec_enable_status;
1412 /**
1413 * FEC re-enable delay when PSR exit.
1414 * unit is 100us, range form 0~255(0xFF).
1415 */
1416 uint8_t fec_enable_delay_in100us;
1417 /**
1418 * PSR control version.
1419 */
1420 uint8_t cmd_version;
1421 /**
1422 * Panel Instance.
1423 * Panel isntance to identify which psr_state to use
1424 * Currently the support is only for 0 or 1
1425 */
1426 uint8_t panel_inst;
1427 /**
1428 * Explicit padding to 4 byte boundary.
1429 */
1430 uint8_t pad3[4];
1431 };
1432
1433 /**
1434 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
1435 */
1436 struct dmub_rb_cmd_psr_copy_settings {
1437 /**
1438 * Command header.
1439 */
1440 struct dmub_cmd_header header;
1441 /**
1442 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
1443 */
1444 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
1445 };
1446
1447 /**
1448 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
1449 */
1450 struct dmub_cmd_psr_set_level_data {
1451 /**
1452 * 16-bit value dicated by driver that will enable/disable different functionality.
1453 */
1454 uint16_t psr_level;
1455 /**
1456 * PSR control version.
1457 */
1458 uint8_t cmd_version;
1459 /**
1460 * Panel Instance.
1461 * Panel isntance to identify which psr_state to use
1462 * Currently the support is only for 0 or 1
1463 */
1464 uint8_t panel_inst;
1465 };
1466
1467 /**
1468 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1469 */
1470 struct dmub_rb_cmd_psr_set_level {
1471 /**
1472 * Command header.
1473 */
1474 struct dmub_cmd_header header;
1475 /**
1476 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
1477 */
1478 struct dmub_cmd_psr_set_level_data psr_set_level_data;
1479 };
1480
1481 struct dmub_rb_cmd_psr_enable_data {
1482 /**
1483 * PSR control version.
1484 */
1485 uint8_t cmd_version;
1486 /**
1487 * Panel Instance.
1488 * Panel isntance to identify which psr_state to use
1489 * Currently the support is only for 0 or 1
1490 */
1491 uint8_t panel_inst;
1492 /**
1493 * Explicit padding to 4 byte boundary.
1494 */
1495 uint8_t pad[2];
1496 };
1497
1498 /**
1499 * Definition of a DMUB_CMD__PSR_ENABLE command.
1500 * PSR enable/disable is controlled using the sub_type.
1501 */
1502 struct dmub_rb_cmd_psr_enable {
1503 /**
1504 * Command header.
1505 */
1506 struct dmub_cmd_header header;
1507
1508 struct dmub_rb_cmd_psr_enable_data data;
1509 };
1510
1511 /**
1512 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1513 */
1514 struct dmub_cmd_psr_set_version_data {
1515 /**
1516 * PSR version that FW should implement.
1517 */
1518 enum psr_version version;
1519 /**
1520 * PSR control version.
1521 */
1522 uint8_t cmd_version;
1523 /**
1524 * Panel Instance.
1525 * Panel isntance to identify which psr_state to use
1526 * Currently the support is only for 0 or 1
1527 */
1528 uint8_t panel_inst;
1529 /**
1530 * Explicit padding to 4 byte boundary.
1531 */
1532 uint8_t pad[2];
1533 };
1534
1535 /**
1536 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
1537 */
1538 struct dmub_rb_cmd_psr_set_version {
1539 /**
1540 * Command header.
1541 */
1542 struct dmub_cmd_header header;
1543 /**
1544 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
1545 */
1546 struct dmub_cmd_psr_set_version_data psr_set_version_data;
1547 };
1548
1549 struct dmub_cmd_psr_force_static_data {
1550 /**
1551 * PSR control version.
1552 */
1553 uint8_t cmd_version;
1554 /**
1555 * Panel Instance.
1556 * Panel isntance to identify which psr_state to use
1557 * Currently the support is only for 0 or 1
1558 */
1559 uint8_t panel_inst;
1560 /**
1561 * Explicit padding to 4 byte boundary.
1562 */
1563 uint8_t pad[2];
1564 };
1565
1566 /**
1567 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
1568 */
1569 struct dmub_rb_cmd_psr_force_static {
1570 /**
1571 * Command header.
1572 */
1573 struct dmub_cmd_header header;
1574 /**
1575 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
1576 */
1577 struct dmub_cmd_psr_force_static_data psr_force_static_data;
1578 };
1579
1580 /**
1581 * Set of HW components that can be locked.
1582 *
1583 * Note: If updating with more HW components, fields
1584 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1585 */
1586 union dmub_hw_lock_flags {
1587 /**
1588 * Set of HW components that can be locked.
1589 */
1590 struct {
1591 /**
1592 * Lock/unlock OTG master update lock.
1593 */
1594 uint8_t lock_pipe : 1;
1595 /**
1596 * Lock/unlock cursor.
1597 */
1598 uint8_t lock_cursor : 1;
1599 /**
1600 * Lock/unlock global update lock.
1601 */
1602 uint8_t lock_dig : 1;
1603 /**
1604 * Triple buffer lock requires additional hw programming to usual OTG master lock.
1605 */
1606 uint8_t triple_buffer_lock : 1;
1607 } bits;
1608
1609 /**
1610 * Union for HW Lock flags.
1611 */
1612 uint8_t u8All;
1613 };
1614
1615 /**
1616 * Instances of HW to be locked.
1617 *
1618 * Note: If updating with more HW components, fields
1619 * in dmub_inbox0_cmd_lock_hw must be updated to match.
1620 */
1621 struct dmub_hw_lock_inst_flags {
1622 /**
1623 * OTG HW instance for OTG master update lock.
1624 */
1625 uint8_t otg_inst;
1626 /**
1627 * OPP instance for cursor lock.
1628 */
1629 uint8_t opp_inst;
1630 /**
1631 * OTG HW instance for global update lock.
1632 * TODO: Remove, and re-use otg_inst.
1633 */
1634 uint8_t dig_inst;
1635 /**
1636 * Explicit pad to 4 byte boundary.
1637 */
1638 uint8_t pad;
1639 };
1640
1641 /**
1642 * Clients that can acquire the HW Lock Manager.
1643 *
1644 * Note: If updating with more clients, fields in
1645 * dmub_inbox0_cmd_lock_hw must be updated to match.
1646 */
1647 enum hw_lock_client {
1648 /**
1649 * Driver is the client of HW Lock Manager.
1650 */
1651 HW_LOCK_CLIENT_DRIVER = 0,
1652 /**
1653 * Invalid client.
1654 */
1655 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
1656 };
1657
1658 /**
1659 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1660 */
1661 struct dmub_cmd_lock_hw_data {
1662 /**
1663 * Specifies the client accessing HW Lock Manager.
1664 */
1665 enum hw_lock_client client;
1666 /**
1667 * HW instances to be locked.
1668 */
1669 struct dmub_hw_lock_inst_flags inst_flags;
1670 /**
1671 * Which components to be locked.
1672 */
1673 union dmub_hw_lock_flags hw_locks;
1674 /**
1675 * Specifies lock/unlock.
1676 */
1677 uint8_t lock;
1678 /**
1679 * HW can be unlocked separately from releasing the HW Lock Mgr.
1680 * This flag is set if the client wishes to release the object.
1681 */
1682 uint8_t should_release;
1683 /**
1684 * Explicit padding to 4 byte boundary.
1685 */
1686 uint8_t pad;
1687 };
1688
1689 /**
1690 * Definition of a DMUB_CMD__HW_LOCK command.
1691 * Command is used by driver and FW.
1692 */
1693 struct dmub_rb_cmd_lock_hw {
1694 /**
1695 * Command header.
1696 */
1697 struct dmub_cmd_header header;
1698 /**
1699 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
1700 */
1701 struct dmub_cmd_lock_hw_data lock_hw_data;
1702 };
1703
1704 /**
1705 * ABM command sub-types.
1706 */
1707 enum dmub_cmd_abm_type {
1708 /**
1709 * Initialize parameters for ABM algorithm.
1710 * Data is passed through an indirect buffer.
1711 */
1712 DMUB_CMD__ABM_INIT_CONFIG = 0,
1713 /**
1714 * Set OTG and panel HW instance.
1715 */
1716 DMUB_CMD__ABM_SET_PIPE = 1,
1717 /**
1718 * Set user requested backklight level.
1719 */
1720 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
1721 /**
1722 * Set ABM operating/aggression level.
1723 */
1724 DMUB_CMD__ABM_SET_LEVEL = 3,
1725 /**
1726 * Set ambient light level.
1727 */
1728 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
1729 /**
1730 * Enable/disable fractional duty cycle for backlight PWM.
1731 */
1732 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
1733 };
1734
1735 /**
1736 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
1737 * Requirements:
1738 * - Padded explicitly to 32-bit boundary.
1739 * - Must ensure this structure matches the one on driver-side,
1740 * otherwise it won't be aligned.
1741 */
1742 struct abm_config_table {
1743 /**
1744 * Gamma curve thresholds, used for crgb conversion.
1745 */
1746 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
1747 /**
1748 * Gamma curve offsets, used for crgb conversion.
1749 */
1750 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
1751 /**
1752 * Gamma curve slopes, used for crgb conversion.
1753 */
1754 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
1755 /**
1756 * Custom backlight curve thresholds.
1757 */
1758 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
1759 /**
1760 * Custom backlight curve offsets.
1761 */
1762 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
1763 /**
1764 * Ambient light thresholds.
1765 */
1766 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
1767 /**
1768 * Minimum programmable backlight.
1769 */
1770 uint16_t min_abm_backlight; // 122B
1771 /**
1772 * Minimum reduction values.
1773 */
1774 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
1775 /**
1776 * Maximum reduction values.
1777 */
1778 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
1779 /**
1780 * Bright positive gain.
1781 */
1782 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
1783 /**
1784 * Dark negative gain.
1785 */
1786 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
1787 /**
1788 * Hybrid factor.
1789 */
1790 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
1791 /**
1792 * Contrast factor.
1793 */
1794 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
1795 /**
1796 * Deviation gain.
1797 */
1798 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
1799 /**
1800 * Minimum knee.
1801 */
1802 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
1803 /**
1804 * Maximum knee.
1805 */
1806 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
1807 /**
1808 * Unused.
1809 */
1810 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
1811 /**
1812 * Explicit padding to 4 byte boundary.
1813 */
1814 uint8_t pad3[3]; // 229B
1815 /**
1816 * Backlight ramp reduction.
1817 */
1818 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
1819 /**
1820 * Backlight ramp start.
1821 */
1822 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
1823 };
1824
1825 /**
1826 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1827 */
1828 struct dmub_cmd_abm_set_pipe_data {
1829 /**
1830 * OTG HW instance.
1831 */
1832 uint8_t otg_inst;
1833
1834 /**
1835 * Panel Control HW instance.
1836 */
1837 uint8_t panel_inst;
1838
1839 /**
1840 * Controls how ABM will interpret a set pipe or set level command.
1841 */
1842 uint8_t set_pipe_option;
1843
1844 /**
1845 * Unused.
1846 * TODO: Remove.
1847 */
1848 uint8_t ramping_boundary;
1849 };
1850
1851 /**
1852 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
1853 */
1854 struct dmub_rb_cmd_abm_set_pipe {
1855 /**
1856 * Command header.
1857 */
1858 struct dmub_cmd_header header;
1859
1860 /**
1861 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
1862 */
1863 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
1864 };
1865
1866 /**
1867 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1868 */
1869 struct dmub_cmd_abm_set_backlight_data {
1870 /**
1871 * Number of frames to ramp to backlight user level.
1872 */
1873 uint32_t frame_ramp;
1874
1875 /**
1876 * Requested backlight level from user.
1877 */
1878 uint32_t backlight_user_level;
1879
1880 /**
1881 * ABM control version.
1882 */
1883 uint8_t version;
1884
1885 /**
1886 * Panel Control HW instance mask.
1887 * Bit 0 is Panel Control HW instance 0.
1888 * Bit 1 is Panel Control HW instance 1.
1889 */
1890 uint8_t panel_mask;
1891
1892 /**
1893 * Explicit padding to 4 byte boundary.
1894 */
1895 uint8_t pad[2];
1896 };
1897
1898 /**
1899 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
1900 */
1901 struct dmub_rb_cmd_abm_set_backlight {
1902 /**
1903 * Command header.
1904 */
1905 struct dmub_cmd_header header;
1906
1907 /**
1908 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
1909 */
1910 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
1911 };
1912
1913 /**
1914 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1915 */
1916 struct dmub_cmd_abm_set_level_data {
1917 /**
1918 * Set current ABM operating/aggression level.
1919 */
1920 uint32_t level;
1921
1922 /**
1923 * ABM control version.
1924 */
1925 uint8_t version;
1926
1927 /**
1928 * Panel Control HW instance mask.
1929 * Bit 0 is Panel Control HW instance 0.
1930 * Bit 1 is Panel Control HW instance 1.
1931 */
1932 uint8_t panel_mask;
1933
1934 /**
1935 * Explicit padding to 4 byte boundary.
1936 */
1937 uint8_t pad[2];
1938 };
1939
1940 /**
1941 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
1942 */
1943 struct dmub_rb_cmd_abm_set_level {
1944 /**
1945 * Command header.
1946 */
1947 struct dmub_cmd_header header;
1948
1949 /**
1950 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
1951 */
1952 struct dmub_cmd_abm_set_level_data abm_set_level_data;
1953 };
1954
1955 /**
1956 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1957 */
1958 struct dmub_cmd_abm_set_ambient_level_data {
1959 /**
1960 * Ambient light sensor reading from OS.
1961 */
1962 uint32_t ambient_lux;
1963
1964 /**
1965 * ABM control version.
1966 */
1967 uint8_t version;
1968
1969 /**
1970 * Panel Control HW instance mask.
1971 * Bit 0 is Panel Control HW instance 0.
1972 * Bit 1 is Panel Control HW instance 1.
1973 */
1974 uint8_t panel_mask;
1975
1976 /**
1977 * Explicit padding to 4 byte boundary.
1978 */
1979 uint8_t pad[2];
1980 };
1981
1982 /**
1983 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1984 */
1985 struct dmub_rb_cmd_abm_set_ambient_level {
1986 /**
1987 * Command header.
1988 */
1989 struct dmub_cmd_header header;
1990
1991 /**
1992 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
1993 */
1994 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
1995 };
1996
1997 /**
1998 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
1999 */
2000 struct dmub_cmd_abm_set_pwm_frac_data {
2001 /**
2002 * Enable/disable fractional duty cycle for backlight PWM.
2003 * TODO: Convert to uint8_t.
2004 */
2005 uint32_t fractional_pwm;
2006
2007 /**
2008 * ABM control version.
2009 */
2010 uint8_t version;
2011
2012 /**
2013 * Panel Control HW instance mask.
2014 * Bit 0 is Panel Control HW instance 0.
2015 * Bit 1 is Panel Control HW instance 1.
2016 */
2017 uint8_t panel_mask;
2018
2019 /**
2020 * Explicit padding to 4 byte boundary.
2021 */
2022 uint8_t pad[2];
2023 };
2024
2025 /**
2026 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2027 */
2028 struct dmub_rb_cmd_abm_set_pwm_frac {
2029 /**
2030 * Command header.
2031 */
2032 struct dmub_cmd_header header;
2033
2034 /**
2035 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
2036 */
2037 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
2038 };
2039
2040 /**
2041 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2042 */
2043 struct dmub_cmd_abm_init_config_data {
2044 /**
2045 * Location of indirect buffer used to pass init data to ABM.
2046 */
2047 union dmub_addr src;
2048
2049 /**
2050 * Indirect buffer length.
2051 */
2052 uint16_t bytes;
2053
2054
2055 /**
2056 * ABM control version.
2057 */
2058 uint8_t version;
2059
2060 /**
2061 * Panel Control HW instance mask.
2062 * Bit 0 is Panel Control HW instance 0.
2063 * Bit 1 is Panel Control HW instance 1.
2064 */
2065 uint8_t panel_mask;
2066
2067 /**
2068 * Explicit padding to 4 byte boundary.
2069 */
2070 uint8_t pad[2];
2071 };
2072
2073 /**
2074 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2075 */
2076 struct dmub_rb_cmd_abm_init_config {
2077 /**
2078 * Command header.
2079 */
2080 struct dmub_cmd_header header;
2081
2082 /**
2083 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
2084 */
2085 struct dmub_cmd_abm_init_config_data abm_init_config_data;
2086 };
2087
2088 /**
2089 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2090 */
2091 struct dmub_cmd_query_feature_caps_data {
2092 /**
2093 * DMUB feature capabilities.
2094 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
2095 */
2096 struct dmub_feature_caps feature_caps;
2097 };
2098
2099 /**
2100 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2101 */
2102 struct dmub_rb_cmd_query_feature_caps {
2103 /**
2104 * Command header.
2105 */
2106 struct dmub_cmd_header header;
2107 /**
2108 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
2109 */
2110 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
2111 };
2112
2113 struct dmub_optc_state {
2114 uint32_t v_total_max;
2115 uint32_t v_total_min;
2116 uint32_t v_total_mid;
2117 uint32_t v_total_mid_frame_num;
2118 uint32_t tg_inst;
2119 uint32_t enable_manual_trigger;
2120 uint32_t clear_force_vsync;
2121 };
2122
2123 struct dmub_rb_cmd_drr_update {
2124 struct dmub_cmd_header header;
2125 struct dmub_optc_state dmub_optc_state_req;
2126 };
2127
2128 /**
2129 * enum dmub_cmd_panel_cntl_type - Panel control command.
2130 */
2131 enum dmub_cmd_panel_cntl_type {
2132 /**
2133 * Initializes embedded panel hardware blocks.
2134 */
2135 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
2136 /**
2137 * Queries backlight info for the embedded panel.
2138 */
2139 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
2140 };
2141
2142 /**
2143 * struct dmub_cmd_panel_cntl_data - Panel control data.
2144 */
2145 struct dmub_cmd_panel_cntl_data {
2146 uint32_t inst; /**< panel instance */
2147 uint32_t current_backlight; /* in/out */
2148 uint32_t bl_pwm_cntl; /* in/out */
2149 uint32_t bl_pwm_period_cntl; /* in/out */
2150 uint32_t bl_pwm_ref_div1; /* in/out */
2151 uint8_t is_backlight_on : 1; /* in/out */
2152 uint8_t is_powered_on : 1; /* in/out */
2153 };
2154
2155 /**
2156 * struct dmub_rb_cmd_panel_cntl - Panel control command.
2157 */
2158 struct dmub_rb_cmd_panel_cntl {
2159 struct dmub_cmd_header header; /**< header */
2160 struct dmub_cmd_panel_cntl_data data; /**< payload */
2161 };
2162
2163 /**
2164 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2165 */
2166 struct dmub_cmd_lvtma_control_data {
2167 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
2168 uint8_t reserved_0[3]; /**< For future use */
2169 uint8_t panel_inst; /**< LVTMA control instance */
2170 uint8_t reserved_1[3]; /**< For future use */
2171 };
2172
2173 /**
2174 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2175 */
2176 struct dmub_rb_cmd_lvtma_control {
2177 /**
2178 * Command header.
2179 */
2180 struct dmub_cmd_header header;
2181 /**
2182 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2183 */
2184 struct dmub_cmd_lvtma_control_data data;
2185 };
2186
2187 /**
2188 * Maximum number of bytes a chunk sent to DMUB for parsing
2189 */
2190 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
2191
2192 /**
2193 * Represent a chunk of CEA blocks sent to DMUB for parsing
2194 */
2195 struct dmub_cmd_send_edid_cea {
2196 uint16_t offset; /**< offset into the CEA block */
2197 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
2198 uint16_t total_length; /**< total length of the CEA block */
2199 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
2200 uint8_t pad[3]; /**< padding and for future expansion */
2201 };
2202
2203 /**
2204 * Result of VSDB parsing from CEA block
2205 */
2206 struct dmub_cmd_edid_cea_amd_vsdb {
2207 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
2208 uint8_t freesync_supported; /**< 1 if Freesync is supported */
2209 uint16_t amd_vsdb_version; /**< AMD VSDB version */
2210 uint16_t min_frame_rate; /**< Maximum frame rate */
2211 uint16_t max_frame_rate; /**< Minimum frame rate */
2212 };
2213
2214 /**
2215 * Result of sending a CEA chunk
2216 */
2217 struct dmub_cmd_edid_cea_ack {
2218 uint16_t offset; /**< offset of the chunk into the CEA block */
2219 uint8_t success; /**< 1 if this sending of chunk succeeded */
2220 uint8_t pad; /**< padding and for future expansion */
2221 };
2222
2223 /**
2224 * Specify whether the result is an ACK/NACK or the parsing has finished
2225 */
2226 enum dmub_cmd_edid_cea_reply_type {
2227 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
2228 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
2229 };
2230
2231 /**
2232 * Definition of a DMUB_CMD__EDID_CEA command.
2233 */
2234 struct dmub_rb_cmd_edid_cea {
2235 struct dmub_cmd_header header; /**< Command header */
2236 union dmub_cmd_edid_cea_data {
2237 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
2238 struct dmub_cmd_edid_cea_output { /**< output with results */
2239 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
2240 union {
2241 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
2242 struct dmub_cmd_edid_cea_ack ack;
2243 };
2244 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
2245 } data; /**< Command data */
2246
2247 };
2248
2249 /**
2250 * union dmub_rb_cmd - DMUB inbox command.
2251 */
2252 union dmub_rb_cmd {
2253 struct dmub_rb_cmd_lock_hw lock_hw;
2254 /**
2255 * Elements shared with all commands.
2256 */
2257 struct dmub_rb_cmd_common cmd_common;
2258 /**
2259 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
2260 */
2261 struct dmub_rb_cmd_read_modify_write read_modify_write;
2262 /**
2263 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
2264 */
2265 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
2266 /**
2267 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
2268 */
2269 struct dmub_rb_cmd_burst_write burst_write;
2270 /**
2271 * Definition of a DMUB_CMD__REG_REG_WAIT command.
2272 */
2273 struct dmub_rb_cmd_reg_wait reg_wait;
2274 /**
2275 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
2276 */
2277 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
2278 /**
2279 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
2280 */
2281 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
2282 /**
2283 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
2284 */
2285 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
2286 /**
2287 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
2288 */
2289 struct dmub_rb_cmd_dpphy_init dpphy_init;
2290 /**
2291 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
2292 */
2293 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
2294 /**
2295 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2296 */
2297 struct dmub_rb_cmd_psr_set_version psr_set_version;
2298 /**
2299 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2300 */
2301 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
2302 /**
2303 * Definition of a DMUB_CMD__PSR_ENABLE command.
2304 */
2305 struct dmub_rb_cmd_psr_enable psr_enable;
2306 /**
2307 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2308 */
2309 struct dmub_rb_cmd_psr_set_level psr_set_level;
2310 /**
2311 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2312 */
2313 struct dmub_rb_cmd_psr_force_static psr_force_static;
2314 /**
2315 * Definition of a DMUB_CMD__PLAT_54186_WA command.
2316 */
2317 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
2318 /**
2319 * Definition of a DMUB_CMD__MALL command.
2320 */
2321 struct dmub_rb_cmd_mall mall;
2322 /**
2323 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
2324 */
2325 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
2326
2327 /**
2328 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
2329 */
2330 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
2331
2332 /**
2333 * Definition of DMUB_CMD__PANEL_CNTL commands.
2334 */
2335 struct dmub_rb_cmd_panel_cntl panel_cntl;
2336 /**
2337 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
2338 */
2339 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
2340
2341 /**
2342 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
2343 */
2344 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
2345
2346 /**
2347 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
2348 */
2349 struct dmub_rb_cmd_abm_set_level abm_set_level;
2350
2351 /**
2352 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
2353 */
2354 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
2355
2356 /**
2357 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
2358 */
2359 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
2360
2361 /**
2362 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
2363 */
2364 struct dmub_rb_cmd_abm_init_config abm_init_config;
2365
2366 /**
2367 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2368 */
2369 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
2370
2371 /**
2372 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2373 */
2374 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
2375
2376 /**
2377 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
2378 */
2379 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
2380 struct dmub_rb_cmd_drr_update drr_update;
2381 /**
2382 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
2383 */
2384 struct dmub_rb_cmd_lvtma_control lvtma_control;
2385 /**
2386 * Definition of a DMUB_CMD__EDID_CEA command.
2387 */
2388 struct dmub_rb_cmd_edid_cea edid_cea;
2389 };
2390
2391 /**
2392 * union dmub_rb_out_cmd - Outbox command
2393 */
2394 union dmub_rb_out_cmd {
2395 /**
2396 * Parameters common to every command.
2397 */
2398 struct dmub_rb_cmd_common cmd_common;
2399 /**
2400 * AUX reply command.
2401 */
2402 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
2403 /**
2404 * HPD notify command.
2405 */
2406 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
2407 };
2408 #pragma pack(pop)
2409
2410
2411 //==============================================================================
2412 //</DMUB_CMD>===================================================================
2413 //==============================================================================
2414 //< DMUB_RB>====================================================================
2415 //==============================================================================
2416
2417 #if defined(__cplusplus)
2418 extern "C" {
2419 #endif
2420
2421 /**
2422 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
2423 */
2424 struct dmub_rb_init_params {
2425 void *ctx; /**< Caller provided context pointer */
2426 void *base_address; /**< CPU base address for ring's data */
2427 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2428 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
2429 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
2430 };
2431
2432 /**
2433 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
2434 */
2435 struct dmub_rb {
2436 void *base_address; /**< CPU address for the ring's data */
2437 uint32_t rptr; /**< Read pointer for consumer in bytes */
2438 uint32_t wrpt; /**< Write pointer for producer in bytes */
2439 uint32_t capacity; /**< Ringbuffer capacity in bytes */
2440
2441 void *ctx; /**< Caller provided context pointer */
2442 void *dmub; /**< Pointer to the DMUB interface */
2443 };
2444
2445 /**
2446 * @brief Checks if the ringbuffer is empty.
2447 *
2448 * @param rb DMUB Ringbuffer
2449 * @return true if empty
2450 * @return false otherwise
2451 */
dmub_rb_empty(struct dmub_rb * rb)2452 static inline bool dmub_rb_empty(struct dmub_rb *rb)
2453 {
2454 return (rb->wrpt == rb->rptr);
2455 }
2456
2457 /**
2458 * @brief Checks if the ringbuffer is full
2459 *
2460 * @param rb DMUB Ringbuffer
2461 * @return true if full
2462 * @return false otherwise
2463 */
dmub_rb_full(struct dmub_rb * rb)2464 static inline bool dmub_rb_full(struct dmub_rb *rb)
2465 {
2466 uint32_t data_count;
2467
2468 if (rb->wrpt >= rb->rptr)
2469 data_count = rb->wrpt - rb->rptr;
2470 else
2471 data_count = rb->capacity - (rb->rptr - rb->wrpt);
2472
2473 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
2474 }
2475
2476 /**
2477 * @brief Pushes a command into the ringbuffer
2478 *
2479 * @param rb DMUB ringbuffer
2480 * @param cmd The command to push
2481 * @return true if the ringbuffer was not full
2482 * @return false otherwise
2483 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)2484 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
2485 const union dmub_rb_cmd *cmd)
2486 {
2487 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2488 const uint8_t *src = (const uint8_t *)cmd;
2489
2490 if (dmub_rb_full(rb))
2491 return false;
2492
2493 // copying data
2494 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2495
2496 rb->wrpt += DMUB_RB_CMD_SIZE;
2497
2498 if (rb->wrpt >= rb->capacity)
2499 rb->wrpt %= rb->capacity;
2500
2501 return true;
2502 }
2503
2504 /**
2505 * @brief Pushes a command into the DMUB outbox ringbuffer
2506 *
2507 * @param rb DMUB outbox ringbuffer
2508 * @param cmd Outbox command
2509 * @return true if not full
2510 * @return false otherwise
2511 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)2512 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
2513 const union dmub_rb_out_cmd *cmd)
2514 {
2515 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
2516 const uint8_t *src = (const uint8_t *)cmd;
2517
2518 if (dmub_rb_full(rb))
2519 return false;
2520
2521 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2522
2523 rb->wrpt += DMUB_RB_CMD_SIZE;
2524
2525 if (rb->wrpt >= rb->capacity)
2526 rb->wrpt %= rb->capacity;
2527
2528 return true;
2529 }
2530
2531 /**
2532 * @brief Returns the next unprocessed command in the ringbuffer.
2533 *
2534 * @param rb DMUB ringbuffer
2535 * @param cmd The command to return
2536 * @return true if not empty
2537 * @return false otherwise
2538 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)2539 static inline bool dmub_rb_front(struct dmub_rb *rb,
2540 union dmub_rb_cmd **cmd)
2541 {
2542 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
2543
2544 if (dmub_rb_empty(rb))
2545 return false;
2546
2547 *cmd = (union dmub_rb_cmd *)rb_cmd;
2548
2549 return true;
2550 }
2551
2552 /**
2553 * @brief Determines the next ringbuffer offset.
2554 *
2555 * @param rb DMUB inbox ringbuffer
2556 * @param num_cmds Number of commands
2557 * @param next_rptr The next offset in the ringbuffer
2558 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)2559 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
2560 uint32_t num_cmds,
2561 uint32_t *next_rptr)
2562 {
2563 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
2564
2565 if (*next_rptr >= rb->capacity)
2566 *next_rptr %= rb->capacity;
2567 }
2568
2569 /**
2570 * @brief Returns a pointer to a command in the inbox.
2571 *
2572 * @param rb DMUB inbox ringbuffer
2573 * @param cmd The inbox command to return
2574 * @param rptr The ringbuffer offset
2575 * @return true if not empty
2576 * @return false otherwise
2577 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)2578 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
2579 union dmub_rb_cmd **cmd,
2580 uint32_t rptr)
2581 {
2582 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
2583
2584 if (dmub_rb_empty(rb))
2585 return false;
2586
2587 *cmd = (union dmub_rb_cmd *)rb_cmd;
2588
2589 return true;
2590 }
2591
2592 /**
2593 * @brief Returns the next unprocessed command in the outbox.
2594 *
2595 * @param rb DMUB outbox ringbuffer
2596 * @param cmd The outbox command to return
2597 * @return true if not empty
2598 * @return false otherwise
2599 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)2600 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
2601 union dmub_rb_out_cmd *cmd)
2602 {
2603 const uint8_t *src = (const uint8_t *)(rb->base_address) + rb->rptr;
2604 uint8_t *dst = (uint8_t *)cmd;
2605
2606 if (dmub_rb_empty(rb))
2607 return false;
2608
2609 // copying data
2610 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
2611
2612 return true;
2613 }
2614
2615 /**
2616 * @brief Removes the front entry in the ringbuffer.
2617 *
2618 * @param rb DMUB ringbuffer
2619 * @return true if the command was removed
2620 * @return false if there were no commands
2621 */
dmub_rb_pop_front(struct dmub_rb * rb)2622 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
2623 {
2624 if (dmub_rb_empty(rb))
2625 return false;
2626
2627 rb->rptr += DMUB_RB_CMD_SIZE;
2628
2629 if (rb->rptr >= rb->capacity)
2630 rb->rptr %= rb->capacity;
2631
2632 return true;
2633 }
2634
2635 /**
2636 * @brief Flushes commands in the ringbuffer to framebuffer memory.
2637 *
2638 * Avoids a race condition where DMCUB accesses memory while
2639 * there are still writes in flight to framebuffer.
2640 *
2641 * @param rb DMUB ringbuffer
2642 */
dmub_rb_flush_pending(const struct dmub_rb * rb)2643 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
2644 {
2645 uint8_t buf[DMUB_RB_CMD_SIZE];
2646 uint32_t rptr = rb->rptr;
2647 uint32_t wptr = rb->wrpt;
2648
2649 while (rptr != wptr) {
2650 const uint8_t *data = (const uint8_t *)rb->base_address + rptr;
2651
2652 dmub_memcpy(buf, data, DMUB_RB_CMD_SIZE);
2653
2654 rptr += DMUB_RB_CMD_SIZE;
2655 if (rptr >= rb->capacity)
2656 rptr %= rb->capacity;
2657 }
2658 }
2659
2660 /**
2661 * @brief Initializes a DMCUB ringbuffer
2662 *
2663 * @param rb DMUB ringbuffer
2664 * @param init_params initial configuration for the ringbuffer
2665 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)2666 static inline void dmub_rb_init(struct dmub_rb *rb,
2667 struct dmub_rb_init_params *init_params)
2668 {
2669 rb->base_address = init_params->base_address;
2670 rb->capacity = init_params->capacity;
2671 rb->rptr = init_params->read_ptr;
2672 rb->wrpt = init_params->write_ptr;
2673 }
2674
2675 /**
2676 * @brief Copies output data from in/out commands into the given command.
2677 *
2678 * @param rb DMUB ringbuffer
2679 * @param cmd Command to copy data into
2680 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)2681 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
2682 union dmub_rb_cmd *cmd)
2683 {
2684 // Copy rb entry back into command
2685 uint8_t *rd_ptr = (rb->rptr == 0) ?
2686 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
2687 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
2688
2689 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
2690 }
2691
2692 #if defined(__cplusplus)
2693 }
2694 #endif
2695
2696 //==============================================================================
2697 //</DMUB_RB>====================================================================
2698 //==============================================================================
2699
2700 #endif /* _DMUB_CMD_H_ */
2701