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Searched refs:mclk_latency_table (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.h212 struct smu10_mclk_latency_table mclk_latency_table; member
Dsmu7_hwmgr.h217 struct smu7_mclk_latency_table mclk_latency_table; member
Dvega10_hwmgr.h315 struct vega10_mclk_latency_table mclk_latency_table; member
Dvega12_hwmgr.h318 struct vega12_mclk_latency_table mclk_latency_table; member
Dsmu7_hwmgr.c3402 for (i = 0; i < data->mclk_latency_table.count; i++) { in smu7_apply_state_adjust_rules()
3403 if (data->mclk_latency_table.entries[i].latency <= latency) { in smu7_apply_state_adjust_rules()
3406 if ((data->mclk_latency_table.entries[i].frequency >= in smu7_apply_state_adjust_rules()
3408 (data->mclk_latency_table.entries[i].frequency <= in smu7_apply_state_adjust_rules()
3410 mclk = data->mclk_latency_table.entries[i].frequency; in smu7_apply_state_adjust_rules()
3415 if ((i >= data->mclk_latency_table.count - 1) && !latency_allowed) { in smu7_apply_state_adjust_rules()
5229 data->mclk_latency_table.count = 0; in smu7_get_mclks_with_latency()
5234 data->mclk_latency_table.entries[data->mclk_latency_table.count].frequency = in smu7_get_mclks_with_latency()
5237 data->mclk_latency_table.entries[data->mclk_latency_table.count].latency = in smu7_get_mclks_with_latency()
5240 data->mclk_latency_table.count++; in smu7_get_mclks_with_latency()
Dvega20_hwmgr.h441 struct vega20_mclk_latency_table mclk_latency_table; member
Dvega12_hwmgr.c1873 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100; in vega12_get_memclocks()
1875 data->mclk_latency_table.entries[i].latency = in vega12_get_memclocks()
1879 clocks->num_levels = data->mclk_latency_table.count = ucount; in vega12_get_memclocks()
2395 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { in vega12_apply_clocks_adjust_rules()
2396 if (data->mclk_latency_table.entries[i].latency <= latency) { in vega12_apply_clocks_adjust_rules()
Dvega10_hwmgr.c3362 for (i = 0; i < data->mclk_latency_table.count; i++) { in vega10_apply_state_adjust_rules()
3363 if ((data->mclk_latency_table.entries[i].latency <= latency) && in vega10_apply_state_adjust_rules()
3364 (data->mclk_latency_table.entries[i].frequency >= in vega10_apply_state_adjust_rules()
3366 (data->mclk_latency_table.entries[i].frequency <= in vega10_apply_state_adjust_rules()
3368 mclk = data->mclk_latency_table.entries[i].frequency; in vega10_apply_state_adjust_rules()
4386 data->mclk_latency_table.entries[j].frequency = in vega10_get_memclocks()
4389 data->mclk_latency_table.entries[j].latency = 25; in vega10_get_memclocks()
4393 clocks->num_levels = data->mclk_latency_table.count = j; in vega10_get_memclocks()
Dvega20_hwmgr.c2842 clocks->num_levels = data->mclk_latency_table.count = count; in vega20_get_memclocks()
2846 data->mclk_latency_table.entries[i].frequency = in vega20_get_memclocks()
2849 data->mclk_latency_table.entries[i].latency = in vega20_get_memclocks()
3796 for (i = 0; i < data->mclk_latency_table.count - 1; i++) { in vega20_apply_clocks_adjust_rules()
3797 if (data->mclk_latency_table.entries[i].latency <= latency) { in vega20_apply_clocks_adjust_rules()
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_smu.h375 struct mclock_latency_table *mclk_latency_table; member