Home
last modified time | relevance | path

Searched refs:merge_3d (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_merge3d.c25 if (idx == m->merge_3d[i].id) { in _merge_3d_offset()
27 b->blk_off = m->merge_3d[i].base; in _merge_3d_offset()
28 b->length = m->merge_3d[i].len; in _merge_3d_offset()
31 return &m->merge_3d[i]; in _merge_3d_offset()
38 static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d, in dpu_hw_merge_3d_setup_3d_mode() argument
45 c = &merge_3d->hw; in dpu_hw_merge_3d_setup_3d_mode()
Ddpu_rm.c141 const struct dpu_merge_3d_cfg *merge_3d = &cat->merge_3d[i]; in dpu_rm_init() local
143 if (merge_3d->id < MERGE_3D_0 || merge_3d->id >= MERGE_3D_MAX) { in dpu_rm_init()
144 DPU_ERROR("skip merge_3d %d with invalid id\n", merge_3d->id); in dpu_rm_init()
147 hw = dpu_hw_merge_3d_init(merge_3d->id, mmio, cat); in dpu_rm_init()
154 rm->merge_3d_blks[merge_3d->id - MERGE_3D_0] = &hw->base; in dpu_rm_init()
172 if (pp->merge_3d && pp->merge_3d < MERGE_3D_MAX) in dpu_rm_init()
173 hw->merge_3d = to_dpu_hw_merge_3d(rm->merge_3d_blks[pp->merge_3d - MERGE_3D_0]); in dpu_rm_init()
Ddpu_encoder_phys_vid.c287 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
288 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; in dpu_encoder_phys_vid_setup_timing_engine()
302 if (phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_setup_timing_engine()
303 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); in dpu_encoder_phys_vid_setup_timing_engine()
447 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) in dpu_encoder_phys_vid_enable()
448 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); in dpu_encoder_phys_vid_enable()
Ddpu_hw_catalog.h539 u32 merge_3d; member
760 const struct dpu_merge_3d_cfg *merge_3d; member
805 #define BLK_MERGE3d(s) ((s)->merge_3d)
Ddpu_hw_ctl.c258 enum dpu_merge_3d merge_3d) in dpu_hw_ctl_update_pending_flush_merge_3d_v1() argument
260 ctx->pending_merge_3d_flush_mask |= BIT(merge_3d - MERGE_3D_0); in dpu_hw_ctl_update_pending_flush_merge_3d_v1()
509 if (cfg->merge_3d) in dpu_hw_ctl_intf_cfg_v1()
511 BIT(cfg->merge_3d - MERGE_3D_0)); in dpu_hw_ctl_intf_cfg_v1()
Ddpu_hw_merge3d.h22 void (*setup_3d_mode)(struct dpu_hw_merge_3d *merge_3d,
Ddpu_hw_pingpong.h138 struct dpu_hw_merge_3d *merge_3d; member
Ddpu_hw_ctl.h47 enum dpu_merge_3d merge_3d; member
Ddpu_hw_catalog.c748 .merge_3d = _merge_3d, \
758 .merge_3d = _merge_3d, \
1200 .merge_3d = sm8150_merge_3d, in sm8150_cfg_init()
1233 .merge_3d = sm8150_merge_3d, in sm8250_cfg_init()