Home
last modified time | relevance | path

Searched refs:misc3 (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_matcher.c96 dr_mask_is_vxlan_gpe_set(struct mlx5dr_match_misc3 *misc3) in dr_mask_is_vxlan_gpe_set() argument
98 return (misc3->outer_vxlan_gpe_vni || in dr_mask_is_vxlan_gpe_set()
99 misc3->outer_vxlan_gpe_next_protocol || in dr_mask_is_vxlan_gpe_set()
100 misc3->outer_vxlan_gpe_flags); in dr_mask_is_vxlan_gpe_set()
114 return dr_mask_is_vxlan_gpe_set(&mask->misc3) && in dr_mask_is_tnl_vxlan_gpe()
126 static bool dr_mask_is_tnl_geneve_tlv_opt(struct mlx5dr_match_misc3 *misc3) in dr_mask_is_tnl_geneve_tlv_opt() argument
128 return misc3->geneve_tlv_option_0_data; in dr_mask_is_tnl_geneve_tlv_opt()
146 static bool dr_mask_is_tnl_gtpu_set(struct mlx5dr_match_misc3 *misc3) in dr_mask_is_tnl_gtpu_set() argument
148 return misc3->gtpu_msg_flags || misc3->gtpu_msg_type || misc3->gtpu_teid; in dr_mask_is_tnl_gtpu_set()
159 return dr_mask_is_tnl_gtpu_set(&mask->misc3) && in dr_mask_is_tnl_gtpu()
[all …]
Ddr_ste_v1.c1567 struct mlx5dr_match_misc3 *misc3 = &value->misc3; in dr_ste_v1_build_icmp_tag() local
1568 bool is_ipv4 = DR_MASK_IS_ICMPV4_SET(misc3); in dr_ste_v1_build_icmp_tag()
1574 icmp_header_data = &misc3->icmpv4_header_data; in dr_ste_v1_build_icmp_tag()
1575 icmp_type = &misc3->icmpv4_type; in dr_ste_v1_build_icmp_tag()
1576 icmp_code = &misc3->icmpv4_code; in dr_ste_v1_build_icmp_tag()
1578 icmp_header_data = &misc3->icmpv6_header_data; in dr_ste_v1_build_icmp_tag()
1579 icmp_type = &misc3->icmpv6_type; in dr_ste_v1_build_icmp_tag()
1580 icmp_code = &misc3->icmpv6_code; in dr_ste_v1_build_icmp_tag()
1630 struct mlx5dr_match_misc3 *misc3 = &value->misc3; in dr_ste_v1_build_eth_l4_misc_tag() local
1633 DR_STE_SET_TAG(eth_l4_misc_v1, tag, seq_num, misc3, inner_tcp_seq_num); in dr_ste_v1_build_eth_l4_misc_tag()
[all …]
Ddr_ste_v0.c1404 struct mlx5dr_match_misc3 *misc_3 = &value->misc3; in dr_ste_v0_build_icmp_tag()
1455 is_ipv4 = DR_MASK_IS_ICMPV4_SET(&mask->misc3); in dr_ste_v0_build_icmp_init()
1494 struct mlx5dr_match_misc3 *misc3 = &value->misc3; in dr_ste_v0_build_eth_l4_misc_tag() local
1497 DR_STE_SET_TAG(eth_l4_misc, tag, seq_num, misc3, inner_tcp_seq_num); in dr_ste_v0_build_eth_l4_misc_tag()
1498 DR_STE_SET_TAG(eth_l4_misc, tag, ack_num, misc3, inner_tcp_ack_num); in dr_ste_v0_build_eth_l4_misc_tag()
1500 DR_STE_SET_TAG(eth_l4_misc, tag, seq_num, misc3, outer_tcp_seq_num); in dr_ste_v0_build_eth_l4_misc_tag()
1501 DR_STE_SET_TAG(eth_l4_misc, tag, ack_num, misc3, outer_tcp_ack_num); in dr_ste_v0_build_eth_l4_misc_tag()
1523 struct mlx5dr_match_misc3 *misc3 = &value->misc3; in dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag() local
1526 outer_vxlan_gpe_flags, misc3, in dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag()
1529 outer_vxlan_gpe_next_protocol, misc3, in dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag()
[all …]
Ddr_rule.c963 s_idx = offsetof(struct mlx5dr_match_param, misc3); in dr_rule_verify()
964 e_idx = min(s_idx + sizeof(param->misc3), value_size); in dr_rule_verify()
Ddr_types.h734 struct mlx5dr_match_misc3 misc3; member
Ddr_ste.c968 dr_ste_copy_mask_misc3(buff, &set_param->misc3); in mlx5dr_ste_copy_param()
/drivers/pcmcia/
Dricoh.h165 u16 misc3; in ricoh_set_clkrun() local
178 misc3 = config_readw(socket, RL5C4XX_MISC3); in ricoh_set_clkrun()
179 if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) { in ricoh_set_clkrun()
187 misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS; in ricoh_set_clkrun()
188 config_writew(socket, RL5C4XX_MISC3, misc3); in ricoh_set_clkrun()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvegam_smumgr.c1253 uint32_t misc3; in vegam_populate_memory_timing_parameters() local
1267 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3); in vegam_populate_memory_timing_parameters()
1273 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3); in vegam_populate_memory_timing_parameters()