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Searched refs:mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h3597 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … macro
Ddcn_2_0_0_offset.h4535 #define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX … macro