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Searched refs:mmCM0_CM_DGAM_RAMA_START_CNTL_R (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h3504 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R … macro
Ddcn_1_0_offset.h3688 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R … macro
Ddcn_2_0_0_offset.h4442 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R … macro