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Searched refs:mmCP_MQD_CONTROL (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dmes_v10_1.c651 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in mes_v10_1_mqd_init()
749 data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in mes_v10_1_queue_init_register()
751 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0); in mes_v10_1_queue_init_register()
Damdgpu_amdkfd_gfx_v7.c228 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_load()
281 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) in kgd_hqd_dump()
Dgfx_v7_0.c2953 mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL); in gfx_v7_0_mqd_init()
3058 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_MQD_CONTROL; mqd_reg++) in gfx_v7_0_mqd_commit()
Dgfx_v9_0.c3540 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v9_0_mqd_init()
3668 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, in gfx_v9_0_kiq_init_register()
Dgfx_v10_0.c6928 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); in gfx_v10_0_compute_mqd_init()
7060 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, in gfx_v10_0_kiq_init_register()
Dgfx_v8_0.c4495 tmp = RREG32(mmCP_MQD_CONTROL); in gfx_v8_0_mqd_init()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_d.h614 #define mmCP_MQD_CONTROL 0x3267 macro
Dgfx_7_0_d.h601 #define mmCP_MQD_CONTROL 0x3267 macro
Dgfx_8_1_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
Dgfx_8_0_d.h667 #define mmCP_MQD_CONTROL 0x3267 macro
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2891 #define mmCP_MQD_CONTROL … macro
Dgc_9_2_1_offset.h3075 #define mmCP_MQD_CONTROL … macro
Dgc_9_1_offset.h3119 #define mmCP_MQD_CONTROL … macro
Dgc_10_1_0_offset.h5355 #define mmCP_MQD_CONTROL … macro
Dgc_10_3_0_offset.h4990 #define mmCP_MQD_CONTROL … macro