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Searched refs:mmDC_I2C_DDC5_HW_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h9278 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro
Ddcn_1_0_offset.h7684 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro
Ddcn_3_0_2_offset.h8964 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro
Ddcn_2_0_0_offset.h10309 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro
Ddcn_3_0_0_offset.h10037 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1653 #define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX … macro