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Searched refs:mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h11154 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h9576 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro
Ddcn_3_0_2_offset.h10892 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h12241 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h12027 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h11321 #define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX … macro