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Searched refs:mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h354 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_3_0_1_offset.h549 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_2_1_0_offset.h609 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_1_0_offset.h979 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_3_0_2_offset.h521 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_2_0_0_offset.h647 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
Ddcn_3_0_0_offset.h532 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h1265 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX … macro