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Searched refs:mmDP1_DP_DPHY_CNTL_BASE_IDX (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h5322 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_3_0_1_offset.h8289 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_2_1_0_offset.h10212 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_1_0_offset.h8688 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_3_0_2_offset.h9904 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_2_0_0_offset.h11303 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
Ddcn_3_0_0_offset.h11039 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h10509 #define mmDP1_DP_DPHY_CNTL_BASE_IDX … macro