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Searched refs:mmHPD4_DC_HPD_INT_STATUS_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_offset.h9426 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro
Ddcn_1_0_offset.h7866 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro
Ddcn_3_0_2_offset.h9102 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro
Ddcn_2_0_0_offset.h10465 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro
Ddcn_3_0_0_offset.h10181 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_12_0_offset.h9751 #define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX … macro