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Searched refs:mmIH_RB_CNTL (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dcik_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_disable_interrupts()
139 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cik_ih_irq_init()
204 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
206 WREG32(mmIH_RB_CNTL, tmp); in cik_ih_get_wptr()
Diceland_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in iceland_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_disable_interrupts()
141 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in iceland_ih_irq_init()
214 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
216 WREG32(mmIH_RB_CNTL, tmp); in iceland_ih_get_wptr()
Dcz_ih.c63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_enable_interrupts()
68 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cz_ih_disable_interrupts()
86 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_disable_interrupts()
141 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in cz_ih_irq_init()
215 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
217 WREG32(mmIH_RB_CNTL, tmp); in cz_ih_get_wptr()
Dtonga_ih.c62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts()
66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts()
83 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_disable_interrupts()
135 WREG32(mmIH_RB_CNTL, ih_rb_cntl); in tonga_ih_irq_init()
218 tmp = RREG32(mmIH_RB_CNTL); in tonga_ih_get_wptr()
220 WREG32(mmIH_RB_CNTL, tmp); in tonga_ih_get_wptr()
Dvega10_ih.c55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
Dnavi10_ih.c57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
Dvega20_ih.c58 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_d.h231 #define mmIH_RB_CNTL 0x0F80 macro
Dosssys_4_0_offset.h120 #define mmIH_RB_CNTL … macro
Dosssys_4_0_1_offset.h120 #define mmIH_RB_CNTL … macro
Dosssys_5_0_0_offset.h120 #define mmIH_RB_CNTL … macro
Dosssys_4_2_0_offset.h122 #define mmIH_RB_CNTL … macro
Doss_2_4_d.h43 #define mmIH_RB_CNTL 0xe30 macro
Doss_3_0_1_d.h43 #define mmIH_RB_CNTL 0xe30 macro
Doss_3_0_d.h43 #define mmIH_RB_CNTL 0xe30 macro
Doss_2_0_d.h43 #define mmIH_RB_CNTL 0xf80 macro