Searched refs:mmIH_RB_RPTR (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | cik_ih.c | 89 WREG32(mmIH_RB_RPTR, 0); in cik_ih_disable_interrupts()
142 WREG32(mmIH_RB_RPTR, 0); in cik_ih_irq_init()
277 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
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| D | iceland_ih.c | 89 WREG32(mmIH_RB_RPTR, 0); in iceland_ih_disable_interrupts()
144 WREG32(mmIH_RB_RPTR, 0); in iceland_ih_irq_init()
268 WREG32(mmIH_RB_RPTR, ih->rptr); in iceland_ih_set_rptr()
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| D | cz_ih.c | 89 WREG32(mmIH_RB_RPTR, 0); in cz_ih_disable_interrupts()
144 WREG32(mmIH_RB_RPTR, 0); in cz_ih_irq_init()
269 WREG32(mmIH_RB_RPTR, ih->rptr); in cz_ih_set_rptr()
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| D | tonga_ih.c | 85 WREG32(mmIH_RB_RPTR, 0); in tonga_ih_disable_interrupts()
142 WREG32(mmIH_RB_RPTR, 0); in tonga_ih_irq_init()
276 WREG32(mmIH_RB_RPTR, ih->rptr); in tonga_ih_set_rptr()
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| D | vega10_ih.c | 57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
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| D | navi10_ih.c | 59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
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| D | vega20_ih.c | 60 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
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| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_1_0_d.h | 232 #define mmIH_RB_RPTR 0x0F82 macro
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| D | osssys_4_0_offset.h | 126 #define mmIH_RB_RPTR … macro
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| D | osssys_4_0_1_offset.h | 126 #define mmIH_RB_RPTR … macro
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| D | osssys_5_0_0_offset.h | 126 #define mmIH_RB_RPTR … macro
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| D | osssys_4_2_0_offset.h | 128 #define mmIH_RB_RPTR … macro
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| D | oss_2_4_d.h | 45 #define mmIH_RB_RPTR 0xe32 macro
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| D | oss_3_0_1_d.h | 45 #define mmIH_RB_RPTR 0xe32 macro
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| D | oss_3_0_d.h | 45 #define mmIH_RB_RPTR 0xe32 macro
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| D | oss_2_0_d.h | 45 #define mmIH_RB_RPTR 0xf82 macro
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