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Searched refs:mmIH_RB_WPTR_ADDR_LO (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_1_0_d.h235 #define mmIH_RB_WPTR_ADDR_LO 0x0F85 macro
Dosssys_4_0_offset.h132 #define mmIH_RB_WPTR_ADDR_LO macro
Dosssys_4_0_1_offset.h132 #define mmIH_RB_WPTR_ADDR_LO macro
Dosssys_5_0_0_offset.h132 #define mmIH_RB_WPTR_ADDR_LO macro
Dosssys_4_2_0_offset.h134 #define mmIH_RB_WPTR_ADDR_LO macro
Doss_2_4_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
Doss_3_0_1_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
Doss_3_0_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
Doss_2_0_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xf85 macro
/drivers/gpu/drm/amd/amdgpu/
Dcik_ih.c136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
Diceland_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
Dcz_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
Dtonga_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
Dvega10_ih.c59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset()
Dnavi10_ih.c61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in navi10_ih_init_register_offset()
Dvega20_ih.c62 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset()