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Searched refs:mode0 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
Drs690.c463 struct drm_display_mode *mode0, in rs690_compute_mode_priority() argument
474 if (mode0 && mode1) { in rs690_compute_mode_priority()
527 } else if (mode0) { in rs690_compute_mode_priority()
586 struct drm_display_mode *mode0 = NULL; in rs690_bandwidth_update() local
600 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs690_bandwidth_update()
613 if (mode0) in rs690_bandwidth_update()
619 rs690_line_buffer_adjust(rdev, mode0, mode1); in rs690_bandwidth_update()
638 mode0, mode1, in rs690_bandwidth_update()
642 mode0, mode1, in rs690_bandwidth_update()
Drv515.c1082 struct drm_display_mode *mode0, in rv515_compute_mode_priority() argument
1093 if (mode0 && mode1) { in rv515_compute_mode_priority()
1146 } else if (mode0) { in rv515_compute_mode_priority()
1205 struct drm_display_mode *mode0 = NULL; in rv515_bandwidth_avivo_update() local
1214 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_avivo_update()
1217 rs690_line_buffer_adjust(rdev, mode0, mode1); in rv515_bandwidth_avivo_update()
1231 mode0, mode1, in rv515_bandwidth_avivo_update()
1235 mode0, mode1, in rv515_bandwidth_avivo_update()
1247 struct drm_display_mode *mode0 = NULL; in rv515_bandwidth_update() local
1256 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rv515_bandwidth_update()
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Drs600.c901 struct drm_display_mode *mode0 = NULL; in rs600_bandwidth_update() local
912 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
916 rs690_line_buffer_adjust(rdev, mode0, mode1); in rs600_bandwidth_update()
Devergreen.c2324 struct drm_display_mode *mode0 = NULL; in evergreen_bandwidth_update() local
2339 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update()
2341 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2343 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
Dsi.c2461 struct drm_display_mode *mode0 = NULL; in dce6_bandwidth_update() local
2476 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in dce6_bandwidth_update()
2478 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update()
2480 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update()
/drivers/rtc/
Drtc-pcf85063.c267 s8 mode0, mode1, reg; in pcf85063_set_offset() local
275 mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0); in pcf85063_set_offset()
278 error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0)); in pcf85063_set_offset()
281 reg = mode0 & ~PCF85063_OFFSET_MODE; in pcf85063_set_offset()
/drivers/block/
Dswim.c228 swim_write(base, mode0, 0xf8); in set_swim_mode()
311 swim_write(base, mode0, EXTERNAL_DRIVE); /* clear drive 1 bit */ in swim_drive()
314 swim_write(base, mode0, INTERNAL_DRIVE); /* clear drive 0 bit */ in swim_drive()
470 swim_write(base, mode0, side); in swim_read_sector()
484 swim_write(base, mode0, MOTON); in swim_read_sector()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c1060 struct drm_display_mode *mode0 = NULL; in dce_v6_0_bandwidth_update() local
1075 mode0 = &adev->mode_info.crtcs[i]->base.mode; in dce_v6_0_bandwidth_update()
1077 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); in dce_v6_0_bandwidth_update()
1079 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); in dce_v6_0_bandwidth_update()