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Searched refs:next_odm_pipe (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1599 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in get_pixel_clock_parameters()
1870 struct pipe_ctx *next_odm_pipe) in dcn20_split_stream_for_odm() argument
1872 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm()
1875 *next_odm_pipe = *prev_odm_pipe; in dcn20_split_stream_for_odm()
1877 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1878 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1879 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1880 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1881 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1882 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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Ddcn20_hwseq.c665 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in dcn20_enable_stream_timing()
716 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in dcn20_enable_stream_timing()
973 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in dcn20_update_odm()
1011 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in dcn20_blank_pixel_data()
1037 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in dcn20_blank_pixel_data()
1293 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe in dcn20_detect_pipe_changes()
1294 && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx) in dcn20_detect_pipe_changes()
1295 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe) in dcn20_detect_pipe_changes()
1296 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe) in dcn20_detect_pipe_changes()
1581 …for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe)… in calculate_vready_offset_for_group()
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Ddcn20_resource.h144 struct pipe_ctx *next_odm_pipe);
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1780 if (pri_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1781 ASSERT(pri_pipe->next_odm_pipe != sec_pipe); in dcn30_split_stream_for_mpc_or_odm()
1782 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1783 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1785 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1786 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1787 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1789 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1790 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1791 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_hwss.c439 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in dp_set_dsc_on_stream()
452 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in dp_set_dsc_on_stream()
459 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in dp_set_dsc_on_stream()
509 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in dp_set_dsc_on_stream()
558 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; in dp_set_dsc_pps_sdp()
Ddc_resource.c678 struct pipe_ctx *next_pipe = pipe->next_odm_pipe; in get_num_odm_splits()
681 next_pipe = next_pipe->next_odm_pipe; in get_num_odm_splits()
780 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) { in calculate_recout()
1044 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe) in resource_build_scaling_params()
1408 …if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe… in dc_add_plane_to_context()
1409 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe; in dc_add_plane_to_context()
1410 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe; in dc_add_plane_to_context()
1414 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe; in dc_add_plane_to_context()
1417 head_pipe = head_pipe->next_odm_pipe; in dc_add_plane_to_context()
1800 odm_pipe = del_pipe->next_odm_pipe; in dc_remove_stream_from_ctx()
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Ddc.c528 param.odm_mode = pipe->next_odm_pipe ? 1:0; in dc_stream_configure_crc()
1868 if (cur_pipe->next_odm_pipe) in dc_copy_state()
1869 cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; in dc_copy_state()
2718 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; in commit_planes_do_stream_update()
2728 odm_pipe = odm_pipe->next_odm_pipe; in commit_planes_do_stream_update()
2846 for (odm_pipe = mpcc_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in commit_planes_for_stream()
3066 if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe || in commit_planes_for_stream()
Ddc_link_dp.c4271 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in set_crtc_test_pattern()
4286 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in set_crtc_test_pattern()
4319 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) in set_crtc_test_pattern()
4323 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) { in set_crtc_test_pattern()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hwseq.c241 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL)) in dcn21_is_abm_supported()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h361 struct pipe_ctx *next_odm_pipe; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c821 …for (other_pipe = pipe->next_odm_pipe; other_pipe != NULL; other_pipe = other_pipe->next_odm_pipe)… in calculate_vready_offset_for_group()
2004 while (pipe->next_odm_pipe) { in get_clock_divider()
2005 pipe = pipe->next_odm_pipe; in get_clock_divider()
3277 bool odm_combine_on = (pipe_ctx->next_odm_pipe != NULL) || in dcn10_set_cursor_position()
3398 if (pipe_ctx->next_odm_pipe) { in dcn10_set_cursor_position()
3400 pipe_ctx->next_odm_pipe->plane_res.scl_data.viewport.y; in dcn10_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hwseq.c608 (pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL)) in dcn31_is_abm_supported()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c1443 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; in apply_single_controller_ctx_to_hw()
1525 odm_pipe = odm_pipe->next_odm_pipe; in apply_single_controller_ctx_to_hw()