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Searched refs:num_pipes (Results 1 – 25 of 52) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_rq_dlg_calc_31.c942 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1050 …n_dst_y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // F… in dml_rq_dlg_get_dlg_params()
1051 …_after_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // F… in dml_rq_dlg_get_dlg_params()
1053 …_l = get_refcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * ref… in dml_rq_dlg_get_dlg_params()
1054 …very_l = get_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * ref… in dml_rq_dlg_get_dlg_params()
1056 …e_l = get_refcyc_per_req_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * ref… in dml_rq_dlg_get_dlg_params()
1057 …ivery_l = get_refcyc_per_req_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * ref… in dml_rq_dlg_get_dlg_params()
1078 …min_ttu_vblank = get_min_ttu_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From … in dml_rq_dlg_get_dlg_params()
1137 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA in dml_rq_dlg_get_dlg_params()
1161 …dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // Fro… in dml_rq_dlg_get_dlg_params()
[all …]
Ddisplay_rq_dlg_calc_31.h61 const unsigned int num_pipes,
/drivers/gpu/drm/omapdrm/
Domap_drv.c135 for (i = 0; i < priv->num_pipes; i++) { in omap_disconnect_pipelines()
146 priv->num_pipes = 0; in omap_disconnect_pipelines()
166 pipe = &priv->pipes[priv->num_pipes++]; in omap_connect_pipelines()
169 if (priv->num_pipes == ARRAY_SIZE(priv->pipes)) { in omap_connect_pipelines()
251 if (priv->num_pipes > num_mgrs || priv->num_pipes > num_ovls) { in omap_modeset_init()
258 plane_crtc_mask = (1 << priv->num_pipes) - 1; in omap_modeset_init()
261 enum drm_plane_type type = i < priv->num_pipes in omap_modeset_init()
280 for (i = 0; i < priv->num_pipes; i++) { in omap_modeset_init()
301 sort(priv->pipes, priv->num_pipes, sizeof(priv->pipes[0]), in omap_modeset_init()
308 for (i = 0; i < priv->num_pipes; ++i) { in omap_modeset_init()
[all …]
Domap_drv.h53 unsigned int num_pipes; member
/drivers/gpu/drm/tidss/
Dtidss_kms.c124 u32 num_pipes = 0; in tidss_dispc_modeset_init() local
181 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
182 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
183 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
184 num_pipes++; in tidss_dispc_modeset_init()
188 crtc_mask = (1 << num_pipes) - 1; in tidss_dispc_modeset_init()
192 for (i = 0; i < num_pipes; ++i) { in tidss_dispc_modeset_init()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c983 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
1141 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
1142 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1217 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1263 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1264 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1280 for (k = 0; k < num_pipes; ++k) { in dml_rq_dlg_get_dlg_params()
1285 for (i = 0; i < num_pipes; i++) { in dml_rq_dlg_get_dlg_params()
1291 for (j = i; j < num_pipes; j++) { in dml_rq_dlg_get_dlg_params()
1338 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
[all …]
Ddisplay_rq_dlg_calc_30.h61 const unsigned int num_pipes,
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c832 const unsigned int num_pipes, in dml_rq_dlg_get_dlg_params() argument
985 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1118 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1146 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1152 num_pipes, in dml_rq_dlg_get_dlg_params()
1157 num_pipes, in dml_rq_dlg_get_dlg_params()
1159 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
[all …]
Ddisplay_rq_dlg_calc_21.h65 const unsigned int num_pipes,
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20.c48 const unsigned int num_pipes,
786 const unsigned int num_pipes, in dml20_rq_dlg_get_dlg_params() argument
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1074 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1075 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1098 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1103 num_pipes, in dml20_rq_dlg_get_dlg_params()
1107 num_pipes, in dml20_rq_dlg_get_dlg_params()
[all …]
Ddisplay_rq_dlg_calc_20v2.c48 const unsigned int num_pipes,
786 const unsigned int num_pipes, in dml20v2_rq_dlg_get_dlg_params() argument
939 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1075 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1076 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1099 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1104 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
1108 num_pipes, in dml20v2_rq_dlg_get_dlg_params()
[all …]
Ddisplay_rq_dlg_calc_20v2.h65 const unsigned int num_pipes,
Ddisplay_rq_dlg_calc_20.h65 const unsigned int num_pipes,
/drivers/gpu/drm/radeon/
Dr420.c93 unsigned num_pipes; in r420_pipes_init() local
104 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; in r420_pipes_init()
109 num_pipes = 1; in r420_pipes_init()
111 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
113 switch (num_pipes) { in r420_pipes_init()
116 num_pipes = 1; in r420_pipes_init()
131 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); in r420_pipes_init()
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.c47 unsigned int num_pipes);
54 unsigned int num_pipes) in dml_get_voltage_level() argument
58 || num_pipes != mode_lib->vba.cache_num_pipes in dml_get_voltage_level()
60 sizeof(display_e2e_pipe_params_st) * num_pipes) != 0; in dml_get_voltage_level()
64 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
65 mode_lib->vba.cache_num_pipes = num_pipes; in dml_get_voltage_level()
80 …ruct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes) \
82 recalculate_params(mode_lib, pipes, num_pipes); \
112 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
115 recalculate_params(mode_lib, pipes, num_pipes); \
[all …]
Ddisplay_mode_vba.h34 …struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
62 …de_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int wh…
115 unsigned int num_pipes);
119 unsigned int num_pipes);
123 unsigned int num_pipes);
127 unsigned int num_pipes);
Ddisplay_mode_lib.h53 const unsigned int num_pipes,
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.h143 int num_pipes, struct dc_crtc_timing_adjust adjust);
145 int num_pipes,
148 int num_pipes, const struct dc_static_screen_params *params);
Ddcn10_dwb.c52 caps->num_pipes = 2; in dwb1_get_caps()
/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer.h96 void (*get_position)(struct pipe_ctx **pipe_ctx, int num_pipes,
114 void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
117 int num_pipes,
/drivers/staging/media/atomisp/pci/
Dsh_css.c131 int num_pipes; member
1476 for (i = 0; i < stream->num_pipes; i++) { in sh_css_invalidate_shading_tables()
1874 for (i = 1; i < stream->num_pipes; i++) in map_sp_threads()
1969 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline_structure()
2111 for (i = 1; i < stream->num_pipes && 0 == err; i++) { in create_host_pipeline()
4551 n = event->pipe->stream->num_pipes; in ia_css_dequeue_psys_event()
4686 for (i = 1; i < stream->num_pipes && 0 == err ; i++) { in sh_css_pipe_start()
4749 for (i = 1; i < stream->num_pipes; i++) { in sh_css_pipe_start()
4922 for (i = 0; i < stream->num_pipes; i++) { in sh_css_pipes_stop()
5021 for (i = 0; i < stream->num_pipes; i++) { in sh_css_pipes_have_stopped()
[all …]
Dia_css_stream.h38 int num_pipes; member
Dia_css_stream_public.h181 int num_pipes,
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c1781 uint8_t i, num_pipes; in dce110_set_displaymarks() local
1784 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { in dce110_set_displaymarks()
1795 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
1796 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
1797 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], in dce110_set_displaymarks()
1798 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
1801 num_pipes++; in dce110_set_displaymarks()
1804 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], in dce110_set_displaymarks()
1805 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], in dce110_set_displaymarks()
1806 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], in dce110_set_displaymarks()
[all …]
/drivers/gpu/drm/mediatek/
Dmtk_drm_drv.h38 unsigned int num_pipes; member

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