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Searched refs:op1 (Results 1 – 8 of 8) sorted by relevance

/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
Dphy_qmath.c13 u16 qm_mulu16(u16 op1, u16 op2) in qm_mulu16() argument
15 return (u16) (((u32) op1 * (u32) op2) >> 16); in qm_mulu16()
26 s16 qm_muls16(s16 op1, s16 op2) in qm_muls16() argument
29 if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) in qm_muls16()
32 result = ((s32) (op1) * (s32) (op2)); in qm_muls16()
42 s32 qm_add32(s32 op1, s32 op2) in qm_add32() argument
45 result = op1 + op2; in qm_add32()
46 if (op1 < 0 && op2 < 0 && result > 0) in qm_add32()
48 else if (op1 > 0 && op2 > 0 && result < 0) in qm_add32()
59 s16 qm_add16(s16 op1, s16 op2) in qm_add16() argument
[all …]
Dphy_qmath.h11 u16 qm_mulu16(u16 op1, u16 op2);
13 s16 qm_muls16(s16 op1, s16 op2);
15 s32 qm_add32(s32 op1, s32 op2);
17 s16 qm_add16(s16 op1, s16 op2);
19 s16 qm_sub16(s16 op1, s16 op2);
/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h253 #define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2)) argument
256 #define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2) argument
257 #define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2) argument
258 #define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1) argument
259 #define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1) argument
265 #define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2) argument
266 #define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2) argument
/drivers/gpu/host1x/
Dcdma.c138 static void host1x_pushbuffer_push(struct push_buffer *pb, u32 op1, u32 op2) in host1x_pushbuffer_push() argument
143 *(p++) = op1; in host1x_pushbuffer_push()
567 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2) in host1x_cdma_push() argument
575 op1, op2); in host1x_cdma_push()
585 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push()
597 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2, in host1x_cdma_push_wide() argument
607 trace_host1x_cdma_push_wide(dev_name(channel->dev), op1, op2, in host1x_cdma_push_wide()
637 host1x_pushbuffer_push(pb, op1, op2); in host1x_cdma_push_wide()
Dcdma.h81 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);
82 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
/drivers/gpu/host1x/hw/
Dchannel_hw.c114 u32 op1 = host1x_opcode_gather_wide(g->words); in submit_gathers() local
117 host1x_cdma_push_wide(cdma, op1, op2, op3, op4); in submit_gathers()
124 u32 op1 = host1x_opcode_gather(g->words); in submit_gathers() local
126 host1x_cdma_push(cdma, op1, op2); in submit_gathers()
/drivers/iommu/
Dmsm_iommu.c28 #define MRC(reg, processor, op1, crn, crm, op2) \ argument
30 " mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
/drivers/tty/serial/
Dmpc52xx_uart.c156 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); in mpc52xx_psc_set_rts()
932 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS); in mpc5125_psc_set_rts()