| /drivers/scsi/cxgbi/cxgb4i/ |
| D | cxgb4i.c | 213 unsigned int opt2; in send_act_open_req() local
226 opt2 = RX_CHANNEL_V(0) | in send_act_open_req()
245 opt2 |= RX_FC_VALID_F; in send_act_open_req()
246 req->opt2 = cpu_to_be32(opt2); in send_act_open_req()
271 opt2 |= T5_ISS_VALID; in send_act_open_req()
272 opt2 |= T5_OPT_2_VALID_F; in send_act_open_req()
274 req->opt2 = cpu_to_be32(opt2); in send_act_open_req()
300 opt2 |= T5_ISS_VALID; in send_act_open_req()
301 opt2 |= RX_FC_DISABLE_F; in send_act_open_req()
302 opt2 |= T5_OPT_2_VALID_F; in send_act_open_req()
[all …]
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| /drivers/infiniband/hw/cxgb4/ |
| D | cm.c | 723 u32 opt2; in send_connect() local
799 opt2 = RX_CHANNEL_V(0) | in send_connect()
803 opt2 |= TSTAMPS_EN_F; in send_connect()
805 opt2 |= SACK_EN_F; in send_connect()
807 opt2 |= WND_SCALE_EN_F; in send_connect()
812 opt2 |= T5_OPT_2_VALID_F; in send_connect()
813 opt2 |= CONG_CNTRL_V(CONG_ALG_TAHOE); in send_connect()
814 opt2 |= T5_ISS_F; in send_connect()
859 req->opt2 = cpu_to_be32(opt2); in send_connect()
866 t5req->opt2 = cpu_to_be32(opt2); in send_connect()
[all …]
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| /drivers/target/iscsi/cxgbit/ |
| D | cxgbit_cm.c | 1137 u32 opt2, hlen; in cxgbit_pass_accept_rpl() local
1175 opt2 = RX_CHANNEL_V(0) | in cxgbit_pass_accept_rpl()
1179 opt2 |= RX_FC_DISABLE_F; in cxgbit_pass_accept_rpl()
1182 opt2 |= TSTAMPS_EN_F; in cxgbit_pass_accept_rpl()
1184 opt2 |= SACK_EN_F; in cxgbit_pass_accept_rpl()
1186 opt2 |= WND_SCALE_EN_F; in cxgbit_pass_accept_rpl()
1198 opt2 |= CCTRL_ECN_V(1); in cxgbit_pass_accept_rpl()
1200 opt2 |= RX_COALESCE_V(3); in cxgbit_pass_accept_rpl()
1201 opt2 |= CONG_CNTRL_V(CONG_ALG_NEWRENO); in cxgbit_pass_accept_rpl()
1203 opt2 |= T5_ISS_F; in cxgbit_pass_accept_rpl()
[all …]
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| /drivers/net/ethernet/chelsio/inline_crypto/chtls/ |
| D | chtls_cm.c | 163 } else if (csk->opt2 & TSTAMPS_EN_F) { in assign_rxopt()
164 csk->opt2 &= ~TSTAMPS_EN_F; in assign_rxopt()
1017 u32 opt2, hlen; in chtls_pass_accept_rpl() local
1045 opt2 = RX_CHANNEL_V(0) | in chtls_pass_accept_rpl()
1049 opt2 |= RX_FC_DISABLE_F; in chtls_pass_accept_rpl()
1051 opt2 |= TSTAMPS_EN_F; in chtls_pass_accept_rpl()
1053 opt2 |= SACK_EN_F; in chtls_pass_accept_rpl()
1059 opt2 |= CCTRL_ECN_V(1); in chtls_pass_accept_rpl()
1060 opt2 |= CONG_CNTRL_V(CONG_ALG_NEWRENO); in chtls_pass_accept_rpl()
1061 opt2 |= T5_ISS_F; in chtls_pass_accept_rpl()
[all …]
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| D | chtls.h | 291 u32 opt2; member
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | t4_msg.h | 462 __be32 opt2; member
497 __be32 opt2; member
512 __be32 opt2; member
528 __be32 opt2; member
541 __be32 opt2; member
558 __be32 opt2; member
572 __be32 opt2; member
587 __be32 opt2; member
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| D | cxgb4_filter.c | 1323 t6req->opt2 = htonl(RSS_QUEUE_VALID_F | in mk_act_open_req6()
1360 t6req->opt2 = htonl(RSS_QUEUE_VALID_F | in mk_act_open_req()
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| D | t4fw_api.h | 614 __be32 opt2; member
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| /drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.c | 598 minfo->values.reg.opt2 = bd->pins[58] << 12; in parse_pins3()
611 minfo->values.reg.opt2 = 0x00000000; in default_pins3()
663 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); in parse_pins5()
699 minfo->values.reg.opt2 = 0x0000AC00; in default_pins5()
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| D | matroxfb_base.h | 480 u_int32_t opt2; member
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| D | matroxfb_DAC1064.c | 756 pci_write_config_dword(minfo->pcidev, PCI_OPTION2_REG, minfo->values.reg.opt2); in g450_memory_init()
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| /drivers/net/can/usb/ |
| D | usb_8dev.c | 172 u8 opt2; /* optional parameter 2 */ member
285 .opt2 = 0 in usb_8dev_cmd_close()
299 .opt2 = 0 in usb_8dev_cmd_version()
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| /drivers/net/fddi/skfp/h/ |
| D | smc.h | 310 #define AIX_EVENT(smc,opt0,opt1,opt2,opt3) /* nothing */ argument
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| /drivers/net/ethernet/chelsio/cxgb3/ |
| D | t3_cpl.h | 568 __be32 opt2; member
585 __be32 opt2; member
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| /drivers/net/ethernet/chelsio/inline_crypto/ch_ktls/ |
| D | chcr_ktls.c | 212 cpl->opt2 = htonl(options); in chcr_ktls_act_open_req()
263 cpl->opt2 = htonl(options); in chcr_ktls_act_open_req6()
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| /drivers/pinctrl/ |
| D | pinctrl-palmas.c | 309 FUNCTION_GROUP(opt2, OPTION2), \
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