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Searched refs:opt_param_mask (Results 1 – 5 of 5) sorted by relevance

/drivers/infiniband/hw/mlx5/
Dqpc.c371 u32 opt_param_mask, void *qpc, in modify_qp_mbox_alloc() argument
390 MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \ in modify_qp_mbox_alloc()
413 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
420 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
427 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
434 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
441 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
447 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
453 opt_param_mask, qpc, uid); in modify_qp_mbox_alloc()
462 int mlx5_core_qp_modify(struct mlx5_ib_dev *dev, u16 opcode, u32 opt_param_mask, in mlx5_core_qp_modify() argument
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Dqp.h18 int mlx5_core_qp_modify(struct mlx5_ib_dev *dev, u16 opcode, u32 opt_param_mask,
Dqp.c4004 MLX5_SET(rts2rts_qp_in, in, opt_param_mask, in __mlx5_ib_qp_set_counter()
/drivers/infiniband/hw/mthca/
Dmthca_qp.c160 __be32 opt_param_mask; member
587 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE); in __mthca_modify_qp()
642 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM); in __mthca_modify_qp()
649 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX); in __mthca_modify_qp()
655 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY | in __mthca_modify_qp()
664 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH); in __mthca_modify_qp()
676 qp_param->opt_param_mask |= in __mthca_modify_qp()
682 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT); in __mthca_modify_qp()
705 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH); in __mthca_modify_qp()
719 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT); in __mthca_modify_qp()
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/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dconn.c752 MLX5_SET(rtr2rts_qp_in, in, opt_param_mask, MLX5_QP_OPTPAR_RNR_TIMEOUT); in mlx5_fpga_conn_rts_qp()