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Searched refs:pfcrx (Results 1 – 5 of 5) sorted by relevance

/drivers/net/ethernet/mellanox/mlx4/
Den_main.c72 MLX4_EN_PARM_INT(pfcrx, 0, "Priority based Flow Control policy on RX[7:0]."
166 params->prof[i].rx_pause = !(pfcrx || pfctx); in mlx4_en_get_profile()
167 params->prof[i].rx_ppp = pfcrx; in mlx4_en_get_profile()
168 params->prof[i].tx_pause = !(pfcrx || pfctx); in mlx4_en_get_profile()
371 if (pfcrx > MAX_PFC_RX) { in mlx4_en_verify_params()
373 pfcrx, MAX_PFC_RX); in mlx4_en_verify_params()
374 pfcrx = 0; in mlx4_en_verify_params()
Dport.c1609 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) in mlx4_SET_PORT_general() argument
1624 context->pprx = (pprx * (!pfcrx)) << 7; in mlx4_SET_PORT_general()
1625 context->pfcrx = pfcrx; in mlx4_SET_PORT_general()
Dmlx4.h804 u8 pfcrx; member
/drivers/net/ethernet/mellanox/mlx5/core/
Dport.c596 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx); in mlx5_set_port_pfc()
618 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx); in mlx5_query_port_pfc()
/drivers/net/ethernet/mellanox/mlxsw/
Dreg.h4890 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);