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Searched refs:pipe_src_w (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_panel.c182 if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w && in intel_pch_panel_fitting()
189 width = crtc_state->pipe_src_w; in intel_pch_panel_fitting()
200 u32 scaled_height = crtc_state->pipe_src_w in intel_pch_panel_fitting()
210 height = scaled_width / crtc_state->pipe_src_w; in intel_pch_panel_fitting()
225 WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w); in intel_pch_panel_fitting()
309 u32 scaled_height = crtc_state->pipe_src_w * in i965_scale_aspect()
319 else if (adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w) in i965_scale_aspect()
330 u32 scaled_height = crtc_state->pipe_src_w * in i9xx_scale_aspect()
358 crtc_state->pipe_src_w); in i9xx_scale_aspect()
361 if (crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) { in i9xx_scale_aspect()
[all …]
Dintel_atomic_plane.c577 clip.x2 = crtc_state->pipe_src_w; in intel_atomic_plane_check_clipping()
583 drm_rect_translate(dst, -crtc_state->pipe_src_w, 0); in intel_atomic_plane_check_clipping()
Dskl_scaler.c199 crtc_state->pipe_src_w, crtc_state->pipe_src_h, in skl_update_scaler_crtc()
660 .x2 = crtc_state->pipe_src_w << 16, in skl_pfit_enable()
Dintel_overlay.c965 if (rec->dst_x < pipe_config->pipe_src_w && in check_overlay_dst()
966 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && in check_overlay_dst()
1161 if (crtc->config->pipe_src_w > 1024 && in intel_overlay_put_image_ioctl()
Dskl_universal_plane.c1270 int pipe_src_w = crtc_state->pipe_src_w; in skl_plane_check_dst_coordinates() local
1282 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { in skl_plane_check_dst_coordinates()
1287 4, pipe_src_w - 4); in skl_plane_check_dst_coordinates()
Dintel_display.c2000 (crtc_state->pipe_src_w > drm_rect_width(&crtc_state->pch_pfit.dst) || in underrun_recovery_supported()
4199 crtc_state->pipe_src_w << 16, in ilk_pipe_pixel_rate()
4290 mode->hdisplay = crtc_state->pipe_src_w << crtc_state->bigjoiner; in intel_crtc_readout_derived_state()
4320 pipe_config->pipe_src_w /= 2; in intel_crtc_compute_config()
4366 if (pipe_config->pipe_src_w & 1) { in intel_crtc_compute_config()
4634 ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); in intel_set_pipe_src_size()
4706 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_src_size()
7585 pipe_config->pipe_src_w, pipe_config->pipe_src_h, in intel_dump_pipe_config()
7889 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
8475 PIPE_CONF_CHECK_I(pipe_src_w); in intel_pipe_config_compare()
Dintel_display_types.h963 int pipe_src_w, pipe_src_h; member
Dintel_display_debugfs.c1029 crtc_state->pipe_src_w, crtc_state->pipe_src_h, in intel_crtc_info()
/drivers/gpu/drm/i915/
Dintel_pm.c1692 width = crtc_state->pipe_src_w; in vlv_compute_wm_level()
2287 int hdisplay = crtc->config->pipe_src_w; in i965_update_wm()
2447 int hdisplay = enabled->config->pipe_src_w; in i9xx_update_wm()