| /drivers/gpu/drm/exynos/ |
| D | exynos_hdmi.c | 81 int pixel_clock; member
160 .pixel_clock = 27000000,
169 .pixel_clock = 27027000,
178 .pixel_clock = 74176000,
187 .pixel_clock = 74250000,
196 .pixel_clock = 148500000,
208 .pixel_clock = 25200000,
217 .pixel_clock = 27000000,
226 .pixel_clock = 27027000,
235 .pixel_clock = 36000000,
[all …]
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| /drivers/media/i2c/et8ek8/ |
| D | et8ek8_mode.c | 46 .pixel_clock = 80000000,
147 .pixel_clock = 80000000,
203 .pixel_clock = 96533333,
259 .pixel_clock = 80000000,
315 .pixel_clock = 80000000,
371 .pixel_clock = 80000000,
426 .pixel_clock = 13333333,
482 .pixel_clock = 49400000,
538 .pixel_clock = 84266667,
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calc_auto.c | 176 …v->byte_per_pixel_in_detc[k], 2.0) / 2.0 * v->v_ratio[k] / 2) / (v->htotal[k] / v->pixel_clock[k]); in mode_support_and_system_configuration()
194 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0; in mode_support_and_system_configuration()
197 v->write_bandwidth[k] = v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 1.5; in mode_support_and_system_configuration()
242 …at[k] == dcn_bw_444 && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) * 4.0 > (v-… in mode_support_and_system_configuration()
245 …== dcn_bw_writeback && v->scaler_rec_out_width[k] / (v->htotal[k] / v->pixel_clock[k]) >dcn_bw_min… in mode_support_and_system_configuration()
265 v->required_output_bw = v->pixel_clock[k] / 2.0; in mode_support_and_system_configuration()
268 v->required_output_bw = v->pixel_clock[k]; in mode_support_and_system_configuration()
272 v->required_output_bw = v->pixel_clock[k] * 3.0 / 2.0; in mode_support_and_system_configuration()
275 v->required_output_bw = v->pixel_clock[k] * 3.0; in mode_support_and_system_configuration()
331 …v->min_dppclk_using_single_dpp[k] = v->pixel_clock[k] *dcn_bw_max3(v->vtaps[k] / 6.0 *dcn_bw_min2(… in mode_support_and_system_configuration()
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_encoders.c | 339 args.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dac()
400 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) in amdgpu_atombios_encoder_setup_dvo()
408 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dvo()
412 if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) in amdgpu_atombios_encoder_setup_dvo()
418 args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dvo()
424 args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dvo()
602 args.v1.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dig_encoder()
610 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) in amdgpu_atombios_encoder_setup_dig_encoder()
637 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dig_encoder()
645 else if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) in amdgpu_atombios_encoder_setup_dig_encoder()
[all …]
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| D | amdgpu_encoders.c | 206 u32 pixel_clock) in amdgpu_dig_monitor_is_duallink() argument
226 if (pixel_clock > 340000) in amdgpu_dig_monitor_is_duallink()
231 if (pixel_clock > 165000) in amdgpu_dig_monitor_is_duallink()
248 if (pixel_clock > 340000) in amdgpu_dig_monitor_is_duallink()
253 if (pixel_clock > 165000) in amdgpu_dig_monitor_is_duallink()
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| /drivers/gpu/drm/vc4/ |
| D | vc4_dpi.c | 92 struct clk *pixel_clock; member
123 clk_disable_unprepare(dpi->pixel_clock); in vc4_dpi_encoder_disable()
207 ret = clk_set_rate(dpi->pixel_clock, mode->clock * 1000); in vc4_dpi_encoder_enable()
211 ret = clk_prepare_enable(dpi->pixel_clock); in vc4_dpi_encoder_enable()
307 dpi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dpi_bind()
308 if (IS_ERR(dpi->pixel_clock)) { in vc4_dpi_bind()
309 ret = PTR_ERR(dpi->pixel_clock); in vc4_dpi_bind()
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| /drivers/gpu/drm/radeon/ |
| D | atombios_encoders.c | 395 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dac_setup()
451 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_tv_setup()
516 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) in atombios_dvo_setup()
524 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dvo_setup()
528 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) in atombios_dvo_setup()
534 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dvo_setup()
540 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dvo_setup()
610 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_digital_setup()
619 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) in atombios_digital_setup()
635 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_digital_setup()
[all …]
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| D | radeon_encoders.c | 365 u32 pixel_clock) in radeon_dig_monitor_is_duallink() argument
387 if (pixel_clock > 340000) in radeon_dig_monitor_is_duallink()
392 if (pixel_clock > 165000) in radeon_dig_monitor_is_duallink()
412 if (pixel_clock > 340000) in radeon_dig_monitor_is_duallink()
417 if (pixel_clock > 165000) in radeon_dig_monitor_is_duallink()
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| /drivers/gpu/drm/amd/display/include/ |
| D | bios_parser_types.h | 119 uint32_t pixel_clock; /* khz */ member
132 uint32_t pixel_clock; /* in KHz */ member
159 uint32_t pixel_clock; member
202 uint32_t pixel_clock; member
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | command_table.c | 241 params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); in encoder_control_digx_v3()
287 params.usPixelClock = cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); in encoder_control_digx_v4()
327 params.ulPixelClock = cntl->pixel_clock / 10; in encoder_control_digx_v5()
490 cpu_to_le16((uint16_t)(cntl->pixel_clock / 20)); in transmitter_control_v2()
496 cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); in transmitter_control_v2()
627 cpu_to_le16((uint16_t)(cntl->pixel_clock / 20)); in transmitter_control_v3()
633 cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); in transmitter_control_v3()
753 cpu_to_le16((uint16_t)(cntl->pixel_clock / 20)); in transmitter_control_v4()
759 cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); in transmitter_control_v4()
832 params.usSymClock = cpu_to_le16((uint16_t) (cntl->pixel_clock / 10)); in transmitter_control_v1_5()
[all …]
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| D | command_table.h | 58 uint32_t pixel_clock,
63 uint32_t pixel_clock,
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| D | command_table2.h | 58 uint32_t pixel_clock,
63 uint32_t pixel_clock,
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| /drivers/gpu/drm/meson/ |
| D | meson_dw_hdmi.c | 293 unsigned int pixel_clock = mode->clock; in meson_hdmi_phy_setup_mode() local
296 if (mode_is_420) pixel_clock /= 2; in meson_hdmi_phy_setup_mode()
300 if (pixel_clock >= 371250) { in meson_hdmi_phy_setup_mode()
304 } else if (pixel_clock >= 297000) { in meson_hdmi_phy_setup_mode()
308 } else if (pixel_clock >= 148500) { in meson_hdmi_phy_setup_mode()
319 if (pixel_clock >= 371250) { in meson_hdmi_phy_setup_mode()
323 } else if (pixel_clock >= 297000) { in meson_hdmi_phy_setup_mode()
334 if (pixel_clock >= 371250) { in meson_hdmi_phy_setup_mode()
339 } else if (pixel_clock >= 297000) { in meson_hdmi_phy_setup_mode()
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| /drivers/media/i2c/ |
| D | ov7251.c | 55 u32 pixel_clock; member
80 struct v4l2_ctrl *pixel_clock; member
531 .pixel_clock = 48000000,
545 .pixel_clock = 48000000,
559 .pixel_clock = 48000000,
1055 ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock, in ov7251_set_format()
1056 new_mode->pixel_clock); in ov7251_set_format()
1195 ret = __v4l2_ctrl_s_ctrl_int64(ov7251->pixel_clock, in ov7251_set_frame_interval()
1196 new_mode->pixel_clock); in ov7251_set_frame_interval()
1359 ov7251->pixel_clock = v4l2_ctrl_new_std(&ov7251->ctrls, in ov7251_probe()
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| D | ov5645.c | 83 u32 pixel_clock; member
102 struct v4l2_ctrl *pixel_clock; member
523 .pixel_clock = 112000000,
531 .pixel_clock = 168000000,
539 .pixel_clock = 168000000,
934 ret = v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock, in ov5645_set_format()
935 new_mode->pixel_clock); in ov5645_set_format()
1158 ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls, in ov5645_probe()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_drrs.c | 57 int pixel_clock; in intel_dp_drrs_compute_config() local
77 pixel_clock = intel_connector->panel.downclock_mode->clock; in intel_dp_drrs_compute_config()
79 pixel_clock /= pipe_config->splitter.link_count; in intel_dp_drrs_compute_config()
81 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, in intel_dp_drrs_compute_config()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 1056 uint32_t pixel_clock) in dce110_link_encoder_enable_tmds_output() argument
1076 cntl.pixel_clock = pixel_clock; in dce110_link_encoder_enable_tmds_output()
1092 uint32_t pixel_clock) in dce110_link_encoder_enable_lvds_output() argument
1109 cntl.pixel_clock = pixel_clock; in dce110_link_encoder_enable_lvds_output()
1145 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_output()
1184 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_mst_output()
1224 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_output()
1263 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_mst_output()
1344 cntl.pixel_clock = link_settings->link_settings.link_rate * in dce110_link_encoder_dp_set_lane_settings()
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| /drivers/phy/ |
| D | phy-core-mipi-dphy.c | 20 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, in phy_mipi_dphy_get_default_config() argument
31 hs_clk_rate = pixel_clock * bpp; in phy_mipi_dphy_get_default_config()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_link_encoder.c | 926 uint32_t pixel_clock) in dcn10_link_encoder_enable_tmds_output() argument
946 cntl.pixel_clock = pixel_clock; in dcn10_link_encoder_enable_tmds_output()
963 uint32_t pixel_clock) in dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa() argument
968 enc, clock_source, color_depth, signal, pixel_clock); in dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa()
998 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_output()
1037 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_mst_output()
1120 cntl.pixel_clock = link_settings->link_settings.link_rate * in dcn10_link_encoder_dp_set_lane_settings()
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| /drivers/media/platform/qcom/camss/ |
| D | camss-vfe.c | 438 u64 pixel_clock[VFE_LINE_NUM_MAX]; in vfe_set_clock_rates() local
444 &pixel_clock[i]); in vfe_set_clock_rates()
446 pixel_clock[i] = 0; in vfe_set_clock_rates()
463 tmp = pixel_clock[j]; in vfe_set_clock_rates()
470 tmp = pixel_clock[j] * bpp / 64; in vfe_set_clock_rates()
521 u64 pixel_clock[VFE_LINE_NUM_MAX]; in vfe_check_clock_rates() local
527 &pixel_clock[i]); in vfe_check_clock_rates()
529 pixel_clock[i] = 0; in vfe_check_clock_rates()
546 tmp = pixel_clock[j]; in vfe_check_clock_rates()
553 tmp = pixel_clock[j] * bpp / 64; in vfe_check_clock_rates()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | link_encoder.h | 148 uint32_t pixel_clock);
157 uint32_t pixel_clock);
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail.h | 13 u16 pixel_clock; member
46 u16 pixel_clock; member
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| /drivers/staging/sm750fb/ |
| D | ddk750_mode.h | 28 unsigned long pixel_clock; member
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| /drivers/video/fbdev/omap/ |
| D | lcd_htcherald.c | 32 .pixel_clock = 6093,
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| D | lcd_palmte.c | 23 .pixel_clock = 12000,
|