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Searched refs:pll_rate (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_lvds_pll.c25 struct pll_rate { struct
34 static const struct pll_rate freqtbl[] = { argument
48 static const struct pll_rate *find_rate(unsigned long rate) in find_rate()
61 const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk); in mpd4_lvds_pll_enable() local
64 DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate); in mpd4_lvds_pll_enable()
66 if (WARN_ON(!pll_rate)) in mpd4_lvds_pll_enable()
71 for (i = 0; pll_rate->conf[i].reg; i++) in mpd4_lvds_pll_enable()
72 mdp4_write(mdp4_kms, pll_rate->conf[i].reg, pll_rate->conf[i].val); in mpd4_lvds_pll_enable()
104 const struct pll_rate *pll_rate = find_rate(rate); in mpd4_lvds_pll_round_rate() local
105 return pll_rate->rate; in mpd4_lvds_pll_round_rate()
/drivers/gpu/drm/msm/hdmi/
Dhdmi_pll_8960.c30 struct pll_rate { struct
40 static const struct pll_rate freqtbl[] = { argument
357 static const struct pll_rate *find_rate(unsigned long rate) in find_rate()
379 const struct pll_rate *pll_rate = find_rate(rate); in hdmi_pll_round_rate() local
381 return pll_rate->rate; in hdmi_pll_round_rate()
388 const struct pll_rate *pll_rate = find_rate(rate); in hdmi_pll_set_rate() local
393 for (i = 0; i < pll_rate->num_reg; i++) in hdmi_pll_set_rate()
394 pll_write(pll, pll_rate->conf[i].reg, pll_rate->conf[i].val); in hdmi_pll_set_rate()
/drivers/gpu/drm/mediatek/
Dmtk_dpi.c434 unsigned long pll_rate; in mtk_dpi_set_display_mode() local
440 pll_rate = vm.pixelclock * factor; in mtk_dpi_set_display_mode()
443 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
445 clk_set_rate(dpi->tvd_clk, pll_rate); in mtk_dpi_set_display_mode()
446 pll_rate = clk_get_rate(dpi->tvd_clk); in mtk_dpi_set_display_mode()
448 vm.pixelclock = pll_rate / factor; in mtk_dpi_set_display_mode()
459 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
/drivers/mfd/
Ddb8500-prcmu.c1396 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate, in pll_rate() function
1452 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1454 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1456 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1484 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX); in armss_rate()
1496 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); in armss_rate()
1523 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK), in dsiclk_rate()
1549 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
1551 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
1555 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW); in prcmu_clock_rate()
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/drivers/clk/spear/
Dclk-vco-pll.c70 unsigned long prate, int index, unsigned long *pll_rate) in pll_calc_rate() argument
78 if (pll_rate) in pll_calc_rate()
79 *pll_rate = (rate / (1 << rtbl[index].p)) * 10000; in pll_calc_rate()
/drivers/phy/mediatek/
Dphy-mtk-hdmi-mt8173.c147 hdmi_phy->pll_rate = rate; in mtk_hdmi_pll_round_rate()
247 return hdmi_phy->pll_rate; in mtk_hdmi_pll_recalc_rate()
Dphy-mtk-hdmi.h36 unsigned long pll_rate; member
/drivers/clk/
Dclk-cdce925.c419 long pll_rate = clk_round_rate(pll, target_rate); in cdce925_clk_best_parent_rate() local
423 if (pll_rate <= 0) in cdce925_clk_best_parent_rate()
425 actual_rate = pll_rate / pdiv_now; in cdce925_clk_best_parent_rate()