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Searched refs:port_sel (Results 1 – 12 of 12) sorted by relevance

/drivers/block/paride/
Dppc6lnx.c24 #define port_sel 8 macro
137 ppc->cur_ctrl |= port_sel; in ppc6_select()
149 ppc->cur_ctrl &= ~port_sel; in ppc6_select()
164 ppc->cur_ctrl |= port_sel; in ppc6_select()
189 ppc->cur_ctrl &= ~(port_sel | port_init); in ppc6_select()
191 ppc->cur_ctrl &= ~port_sel; in ppc6_select()
213 ppc->cur_ctrl |= port_sel; in ppc6_deselect()
219 outb((ppc->org_ctrl | port_sel), ppc->lpt_addr + 2); in ppc6_deselect()
/drivers/scsi/cxlflash/
Dlunmgt.c253 lli->port_sel |= CHAN2PORTMASK(chan); in cxlflash_manage_lun()
265 lli->port_sel &= ~CHAN2PORTMASK(chan); in cxlflash_manage_lun()
266 if (lli->port_sel == 0U) in cxlflash_manage_lun()
272 __func__, lli->port_sel, chan, lli->lun_id[chan]); in cxlflash_manage_lun()
Dvlun.c577 lli->port_sel)); in grow_lxt()
850 if (lli->port_sel & (1 << k)) { in cxlflash_restore_luntable()
900 nports = get_num_ports(lli->port_sel); in init_luntable()
913 if (!(lli->port_sel & (1 << k))) in init_luntable()
926 if (!(lli->port_sel & (1 << k))) in init_luntable()
940 chan = PORTMASK2CHAN(lli->port_sel); in init_luntable()
1059 if (get_num_ports(lli->port_sel) > 1) in cxlflash_disk_virtual_open()
Dsislite.h48 u32 port_sel; /* this is a selection mask: member
523 u8 port_sel; member
Dsuperpipe.h58 u32 port_sel; /* What port to use for this LUN */ member
Dmain.c496 cmd->rcb.port_sel = CHAN2PORTMASK(sdev->channel); in send_tmf()
624 cmd->rcb.port_sel = CHAN2PORTMASK(scp->device->channel); in cxlflash_queuecommand()
1228 u64 port_sel; in afu_link_reset() local
1231 port_sel = readq_be(&afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1232 port_sel &= ~(1ULL << port); in afu_link_reset()
1233 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1249 port_sel |= (1ULL << port); in afu_link_reset()
1250 writeq_be(port_sel, &afu->afu_map->global.regs.afu_port_sel); in afu_link_reset()
1253 dev_dbg(dev, "%s: returning port_sel=%016llx\n", __func__, port_sel); in afu_link_reset()
Dsuperpipe.c526 u32 port_sel) in rht_format1() argument
550 dummy.port_sel = port_sel; in rht_format1()
/drivers/gpu/drm/i915/display/
Dintel_pps.c260 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe() local
263 if (port_sel != PANEL_PORT_SELECT_VLV(port)) in vlv_initial_pps_pipe()
1254 u32 pp_on, pp_off, port_sel = 0; in pps_init_registers() local
1299 port_sel = PANEL_PORT_SELECT_VLV(port); in pps_init_registers()
1303 port_sel = PANEL_PORT_SELECT_DPA; in pps_init_registers()
1306 port_sel = PANEL_PORT_SELECT_DPC; in pps_init_registers()
1309 port_sel = PANEL_PORT_SELECT_DPD; in pps_init_registers()
1317 pp_on |= port_sel; in pps_init_registers()
Dintel_display.c405 u32 port_sel; in assert_panel_unlocked() local
408 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
410 switch (port_sel) { in assert_panel_unlocked()
424 MISSING_CASE(port_sel); in assert_panel_unlocked()
432 u32 port_sel; in assert_panel_unlocked() local
435 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
438 port_sel != PANEL_PORT_SELECT_LVDS); in assert_panel_unlocked()
/drivers/ata/
Dpata_icside.c56 u8 port_sel; member
240 writeb(state->port[ap->port_no].port_sel, state->ioc_base); in pata_icside_bmdma_setup()
427 state->port[0].port_sel = sel; in pata_icside_register_v6()
428 state->port[1].port_sel = sel | 1; in pata_icside_register_v6()
/drivers/i2c/busses/
Di2c-piix4.c392 u8 smb_en, smb_en_status, port_sel; in piix4_setup_sb800() local
482 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); in piix4_setup_sb800()
483 piix4_port_sel_sb800 = (port_sel & 0x01) ? in piix4_setup_sb800()
/drivers/rapidio/
Drio.c1485 u32 port_sel = RIO_INVALID_ROUTE; in rio_std_route_clr_table() local
1501 port_sel = (RIO_INVALID_ROUTE << 24) | in rio_std_route_clr_table()
1513 port_sel); in rio_std_route_clr_table()