| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ras_eeprom.c | 521 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
529 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
532 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
770 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_eeprom_size_read() local
771 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read()
778 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
827 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size() local
829 struct dentry *de = ras->de_ras_eeprom_table; in amdgpu_ras_debugfs_set_ret_size()
839 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_table_read() local
840 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read()
[all …]
|
| D | amdgpu_ras.h | 476 #define amdgpu_ras_get_context(adev) ((adev)->psp.ras_context.ras)
477 #define amdgpu_ras_set_context(adev, ras_con) ((adev)->psp.ras_context.ras = (ras_con))
483 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_is_supported() local
487 return ras && (adev->ras_enabled & (1 << block)); in amdgpu_ras_is_supported()
509 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_reset_gpu() local
511 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) in amdgpu_ras_reset_gpu()
512 schedule_work(&ras->recovery_work); in amdgpu_ras_reset_gpu()
|
| D | psp_v11_0.c | 159 adev->psp.ras.feature_version = le32_to_cpu(ta_hdr->ras.fw_version); in psp_v11_0_init_microcode()
160 adev->psp.ras.size_bytes = le32_to_cpu(ta_hdr->ras.size_bytes); in psp_v11_0_init_microcode()
161 adev->psp.ras.start_addr = (uint8_t *)adev->psp.xgmi.start_addr + in psp_v11_0_init_microcode()
162 le32_to_cpu(ta_hdr->ras.offset_bytes); in psp_v11_0_init_microcode()
|
| D | amdgpu_ras.c | 1731 struct amdgpu_ras *ras = in amdgpu_ras_do_recovery() local
1734 struct amdgpu_device *adev = ras->adev; in amdgpu_ras_do_recovery()
1737 if (!ras->disable_ras_err_cnt_harvest) { in amdgpu_ras_do_recovery()
1758 if (amdgpu_device_should_recover_gpu(ras->adev)) in amdgpu_ras_do_recovery()
1759 amdgpu_device_gpu_recover(ras->adev, NULL); in amdgpu_ras_do_recovery()
1760 atomic_set(&ras->in_recovery, 0); in amdgpu_ras_do_recovery()
1870 &adev->psp.ras_context.ras->eeprom_control; in amdgpu_ras_load_bad_pages()
2066 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_request_reset_on_boot() local
2068 if (!ras) in amdgpu_ras_request_reset_on_boot()
2071 ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; in amdgpu_ras_request_reset_on_boot()
|
| D | amdgpu_psp.h | 164 struct amdgpu_ras *ras; member
330 struct psp_bin_desc ras; member
|
| D | soc15.c | 527 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset() local
531 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
539 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
550 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method() local
586 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
|
| D | amdgpu_psp.c | 1340 psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes); in psp_ras_load()
1353 psp->ras.size_bytes, in psp_ras_load()
1526 if (!adev->psp.ras.size_bytes || in psp_ras_initialize()
1527 !adev->psp.ras.start_addr) { in psp_ras_initialize()
2482 struct amdgpu_ras *ras = psp->ras_context.ras; in psp_load_smu_fw() local
2488 ras && adev->ras_enabled && in psp_load_smu_fw()
3304 psp->ras.feature_version = le32_to_cpu(desc->fw_version); in parse_ta_bin_descriptor()
3305 psp->ras.size_bytes = le32_to_cpu(desc->size_bytes); in parse_ta_bin_descriptor()
3306 psp->ras.start_addr = ucode_start_addr; in parse_ta_bin_descriptor()
|
| D | nbio_v7_4.c | 355 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in nbio_v7_4_handle_ras_controller_intr_no_bifring() local
373 if (!ras->disable_ras_err_cnt_harvest) { in nbio_v7_4_handle_ras_controller_intr_no_bifring()
|
| D | amdgpu_kms.c | 357 fw_info->feature = adev->psp.ras.feature_version; in amdgpu_firmware_info()
1064 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_info_ioctl() local
1067 if (!ras) in amdgpu_info_ioctl()
1069 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; in amdgpu_info_ioctl()
|
| D | amdgpu_ucode.h | 140 struct psp_fw_legacy_bin_desc ras; member
|
| D | amdgpu_virt.c | 537 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ras.feature_version); in amdgpu_virt_populate_vf2pf_ucode_info()
|
| D | amdgpu_ucode.c | 529 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras.feature_version);
|
| D | amdgpu_device.c | 5505 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_device_baco_enter() local
5510 if (ras && adev->ras_enabled && in amdgpu_device_baco_enter()
5520 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_device_baco_exit() local
5530 if (ras && adev->ras_enabled && in amdgpu_device_baco_exit()
|
| /drivers/edac/ |
| D | i5000_edac.c | 471 int ras, cas; in i5000_process_fatal_error_info() local
484 ras = NREC_RAS(info->nrecmemb); in i5000_process_fatal_error_info()
489 rdwr ? "Write" : "Read", ras, cas); in i5000_process_fatal_error_info()
525 bank, ras, cas, allErrors, specific); in i5000_process_fatal_error_info()
556 int ras, cas; in i5000_process_nonfatal_error_info() local
579 ras = NREC_RAS(info->nrecmemb); in i5000_process_nonfatal_error_info()
584 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
624 rank, bank, ras, cas, ue_errors, specific); in i5000_process_nonfatal_error_info()
651 ras = REC_RAS(info->recmemb); in i5000_process_nonfatal_error_info()
656 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
[all …]
|
| D | i5100_edac.c | 438 unsigned ras, in i5100_handle_ce() argument
446 bank, cas, ras); in i5100_handle_ce()
460 unsigned ras, in i5100_handle_ue() argument
468 bank, cas, ras); in i5100_handle_ue()
488 unsigned ras; in i5100_read_log() local
508 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
517 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
530 ras = i5100_nrecmemb_ras(dw2); in i5100_read_log()
539 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
|
| D | i5400_edac.c | 522 int ras, cas; in i5400_proccess_non_recoverable_info() local
548 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
553 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
561 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
586 int ras, cas; in i5400_process_nonfatal_error_info() local
618 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
626 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
632 branch >> 1, bank, rdwr_str(rdwr), ras, cas, in i5400_process_nonfatal_error_info()
|
| D | i7300_edac.c | 411 unsigned branch, channel, bank, rank, cas, ras; in i7300_process_fbd_error() local
439 ras = NRECMEMB_RAS(value); in i7300_process_fbd_error()
447 bank, ras, cas, errors, specific); in i7300_process_fbd_error()
478 ras = RECMEMB_RAS(value); in i7300_process_fbd_error()
494 bank, ras, cas, errors, specific); in i7300_process_fbd_error()
|
| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega20_baco.c | 77 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
88 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
|
| /drivers/ras/ |
| D | Makefile | 2 obj-$(CONFIG_RAS) += ras.o
|
| D | ras.c | 14 #define TRACE_INCLUDE_PATH ../../include/ras
|
| D | Kconfig | 34 source "arch/x86/ras/Kconfig"
|
| /drivers/ |
| D | Makefile | 173 obj-$(CONFIG_RAS) += ras/
|
| D | Kconfig | 202 source "drivers/ras/Kconfig"
|
| /drivers/scsi/hisi_sas/ |
| D | hisi_sas_v3_hw.c | 3353 const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg; in debugfs_snapshot_ras_reg_v3_hw() local
3356 for (i = 0; i < ras->count; i++, databuf++) in debugfs_snapshot_ras_reg_v3_hw()
3357 *databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off); in debugfs_snapshot_ras_reg_v3_hw()
3454 struct hisi_sas_debugfs_regs *ras = s->private; in debugfs_ras_v3_hw_show() local
3456 debugfs_print_reg_v3_hw(ras->data, s, in debugfs_ras_v3_hw_show()
|
| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | smu_v11_0.c | 1629 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in smu_v11_0_baco_set_state() local
1656 if (!ras || !adev->ras_enabled || in smu_v11_0_baco_set_state()
|