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Searched refs:raw_reg_read (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/gt/
Dintel_gt_irq.c41 ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank)); in gen11_gt_engine_identity()
118 intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); in gen11_gt_bank_handler()
152 dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank)); in gen11_gt_reset_one_iir()
306 iir = raw_reg_read(regs, GEN8_GT_IIR(0)); in gen8_gt_irq_handler()
317 iir = raw_reg_read(regs, GEN8_GT_IIR(1)); in gen8_gt_irq_handler()
328 iir = raw_reg_read(regs, GEN8_GT_IIR(3)); in gen8_gt_irq_handler()
337 iir = raw_reg_read(regs, GEN8_GT_IIR(2)); in gen8_gt_irq_handler()
/drivers/gpu/drm/i915/
Di915_irq.c2159 de_ier = raw_reg_read(regs, DEIER); in ilk_irq_handler()
2168 sde_ier = raw_reg_read(regs, SDEIER); in ilk_irq_handler()
2174 gt_iir = raw_reg_read(regs, GTIIR); in ilk_irq_handler()
2184 de_iir = raw_reg_read(regs, DEIIR); in ilk_irq_handler()
2195 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR); in ilk_irq_handler()
2600 return raw_reg_read(regs, GEN8_MASTER_IRQ); in gen8_master_intr_disable()
2649 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR); in gen11_gu_misc_irq_ack()
2673 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ); in gen11_master_intr_disable()
2685 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL); in gen11_display_irq_handler()
2743 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); in dg1_master_intr_disable()
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Dintel_uncore.h438 #define raw_reg_read(base, reg) \ macro