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Searched refs:readw (Results 1 – 25 of 260) sorted by relevance

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/drivers/scsi/qla4xxx/
Dql4_dbg.c46 readw(&ha->reg->mailbox[i])); in qla4xxx_dump_registers()
51 readw(&ha->reg->flash_address)); in qla4xxx_dump_registers()
54 readw(&ha->reg->flash_data)); in qla4xxx_dump_registers()
57 readw(&ha->reg->ctrl_status)); in qla4xxx_dump_registers()
62 readw(&ha->reg->u1.isp4010.nvram)); in qla4xxx_dump_registers()
66 readw(&ha->reg->u1.isp4022.intr_mask)); in qla4xxx_dump_registers()
69 readw(&ha->reg->u1.isp4022.nvram)); in qla4xxx_dump_registers()
72 readw(&ha->reg->u1.isp4022.semaphore)); in qla4xxx_dump_registers()
76 readw(&ha->reg->req_q_in)); in qla4xxx_dump_registers()
79 readw(&ha->reg->rsp_q_out)); in qla4xxx_dump_registers()
[all …]
/drivers/scsi/arm/
Dcumana_1.c130 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
131 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
132 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
133 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
134 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
135 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
136 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
137 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
/drivers/net/ethernet/stmicro/stmmac/
Daltr_tse_pcs.c67 val = readw(base + TSE_PCS_CONTROL_REG); in tse_pcs_reset()
72 val = readw(base + TSE_PCS_CONTROL_REG); in tse_pcs_reset()
112 val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); in pcs_link_timer_callback()
133 val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); in auto_nego_timer_callback()
138 val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); in auto_nego_timer_callback()
177 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in auto_nego_timer_callback()
206 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
210 val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); in tse_pcs_fix_mac_speed()
214 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
224 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
[all …]
/drivers/input/keyboard/
Dimx_keypad.c93 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
97 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
103 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
112 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
126 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
134 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
258 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
262 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
276 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
280 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
[all …]
/drivers/tty/
Dmoxa.c238 while (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
241 if (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
263 ret = readw(ofsAddr + FuncArg); in moxafuncret()
273 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
274 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
275 mask = readw(ofsAddr + RX_mask); in moxa_low_water_check()
474 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
479 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
484 tmp = readw(baseAddr + C320_key); in moxa_load_bios()
487 tmp = readw(baseAddr + C320_status); in moxa_load_bios()
[all …]
/drivers/i2c/busses/
Di2c-wmt.c98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy()
149 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
170 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
188 val = readw(i2c_dev->base + REG_CSR); in wmt_i2c_write()
228 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
232 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
237 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
243 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
260 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
[all …]
/drivers/rtc/
Drtc-mxc.c97 day = readw(ioaddr + RTC_DAYR); in get_alarm_or_time()
98 hr_min = readw(ioaddr + RTC_HOURMIN); in get_alarm_or_time()
99 sec = readw(ioaddr + RTC_SECOND); in get_alarm_or_time()
102 day = readw(ioaddr + RTC_DAYALARM); in get_alarm_or_time()
103 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; in get_alarm_or_time()
104 sec = readw(ioaddr + RTC_ALRM_SEC); in get_alarm_or_time()
162 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); in rtc_update_alarm()
175 reg = readw(ioaddr + RTC_RTCIENR); in mxc_rtc_irq_enable()
196 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); in mxc_rtc_interrupt()
265 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; in mxc_rtc_read_alarm()
[all …]
/drivers/media/pci/netup_unidvb/
Dnetup_unidvb_i2c.c72 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
95 tmp = readw(&i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_interrupt()
103 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
135 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); in netup_i2c_fifo_tx()
148 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
156 u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f; in netup_i2c_fifo_rx()
172 writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_rx()
180 u16 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_start_xfer()
188 __func__, readw(&i2c->regs->length), in netup_i2c_start_xfer()
189 readw(&i2c->regs->twi_addr_ctrl1), in netup_i2c_start_xfer()
[all …]
Dnetup_unidvb_ci.c60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
66 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
91 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_reset()
99 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_ci_slot_reset()
123 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_poll_ci_slot_status()
124 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_poll_ci_slot_status()
Dnetup_unidvb_spi.c78 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
86 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
136 __func__, readw(&spi->regs->control_stat)); in netup_spi_transfer()
232 reg = readw(&spi->regs->control_stat); in netup_spi_release()
234 reg = readw(&spi->regs->control_stat); in netup_spi_release()
/drivers/pci/
Drom.c94 if (readw(image) != 0xAA55) { in pci_get_rom_size()
96 readw(image)); in pci_get_rom_size()
100 pds = image + readw(image + 24); in pci_get_rom_size()
107 length = readw(pds + 16); in pci_get_rom_size()
113 if (readw(image) != 0xAA55) { in pci_get_rom_size()
/drivers/net/ethernet/packetengines/
Dhamachi.c749 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32, in hamachi_init_one()
751 readw(ioaddr + ANLinkPartnerAbility)); in hamachi_init_one()
824 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
829 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
831 return readw(ioaddr + MII_Rd_Data); in mdio_read()
842 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
849 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
890 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6; in hamachi_open()
984 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); in hamachi_open()
1034 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus), in hamachi_timer()
[all …]
/drivers/comedi/drivers/
Ddaqboard2000.c312 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in db2k_ai_status()
373 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in db2k_ai_insn_read()
389 status = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_ao_eoc()
471 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS); in db2k_wait_cpld_init()
487 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_wait_cpld_txready()
508 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT)) in db2k_write_cpld()
574 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_load_firmware()
631 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
641 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
675 return readw(dev->mmio + iobase + port * 2); in db2k_8255_cb()
Dme_daq.c203 val = readw(mmio_porta); in me_dio_insn_bits()
208 val |= (readw(mmio_portb) << 16); in me_dio_insn_bits()
222 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
274 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
282 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata; in me_ai_insn_read()
323 readw(dev->mmio + ME_DAC_CTRL_REG); in me_ao_insn_write()
334 readw(dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
352 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET); in me2600_xilinx_download()
/drivers/dma/ioat/
Ddca.c137 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_add_requester()
163 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_remove_requester()
218 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_count_dca_slots()
270 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat_dca_init()
289 csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); in ioat_dca_init()
295 pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); in ioat_dca_init()
/drivers/pwm/
Dpwm-tiecap.c75 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
97 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
116 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
144 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_enable()
160 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_disable()
279 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); in ecap_pwm_save_context()
/drivers/pci/controller/
Dpci-v3-semi.c444 status = readw(v3->base + V3_PCI_STAT); in v3_irq()
781 if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK) in v3_pci_probe()
785 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
790 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
795 val = readw(v3->base + V3_PCI_CFG); in v3_pci_probe()
800 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
808 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
856 val = readw(v3->base + V3_LB_CFG); in v3_pci_probe()
870 val = readw(v3->base + V3_PCI_CMD); in v3_pci_probe()
881 val = readw(v3->base + V3_SYSTEM); in v3_pci_probe()
[all …]
/drivers/spi/
Dspi-pl022.c444 tmp = readw(SSP_CSR(pl022->virtbase)); in internal_cs_control()
523 writew((readw(SSP_CR1(pl022->virtbase)) & in giveback()
539 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in flush()
540 readw(SSP_DR(pl022->virtbase)); in flush()
541 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--); in flush()
682 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
686 readw(SSP_DR(pl022->virtbase)); in readwriter()
690 readw(SSP_DR(pl022->virtbase)) & 0xFFU; in readwriter()
694 (u16) readw(SSP_DR(pl022->virtbase)); in readwriter()
731 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE) in readwriter()
[all …]
/drivers/gpu/drm/nouveau/dispnv50/
Dheadc57d.c147 writew(readw(mem - 8), mem + 0); in headc57d_olut_load_8()
148 writew(readw(mem - 6), mem + 2); in headc57d_olut_load_8()
149 writew(readw(mem - 4), mem + 4); in headc57d_olut_load_8()
167 writew(readw(mem - 8), mem + 0); in headc57d_olut_load()
168 writew(readw(mem - 6), mem + 2); in headc57d_olut_load()
169 writew(readw(mem - 4), mem + 4); in headc57d_olut_load()
/drivers/watchdog/
Dmenz69_wdt.c39 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
51 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
64 val = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_ping()
80 reg = readw(drv->base + MEN_Z069_WVR); in men_z069_wdt_set_timeout()
/drivers/atm/
Diphase.c1034 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1036 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1037 readw(iadev->seg_ram+tcq_wr_ptr-2));
1040 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1041 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1046 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1068 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1073 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1074 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1077 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
[all …]
/drivers/usb/musb/
Dsunxi.c184 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); in sunxi_musb_interrupt()
188 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); in sunxi_musb_interrupt()
529 return readw(addr + SUNXI_MUSB_INTRTX); in sunxi_musb_readw()
531 return readw(addr + SUNXI_MUSB_INTRRX); in sunxi_musb_readw()
533 return readw(addr + SUNXI_MUSB_INTRTXE); in sunxi_musb_readw()
535 return readw(addr + SUNXI_MUSB_INTRRXE); in sunxi_musb_readw()
537 return readw(addr + SUNXI_MUSB_FRAME); in sunxi_musb_readw()
539 return readw(addr + SUNXI_MUSB_TXFIFOADD); in sunxi_musb_readw()
541 return readw(addr + SUNXI_MUSB_RXFIFOADD); in sunxi_musb_readw()
551 return readw(addr + offset); in sunxi_musb_readw()
[all …]
/drivers/ata/
Dsata_vsc.c189 tf->device = readw(ioaddr->device_addr); in vsc_sata_tf_read()
190 error = readw(ioaddr->error_addr); in vsc_sata_tf_read()
191 nsect = readw(ioaddr->nsect_addr); in vsc_sata_tf_read()
192 lbal = readw(ioaddr->lbal_addr); in vsc_sata_tf_read()
193 lbam = readw(ioaddr->lbam_addr); in vsc_sata_tf_read()
194 lbah = readw(ioaddr->lbah_addr); in vsc_sata_tf_read()
/drivers/hsi/controllers/
Domap_ssi_core.c81 readw(gdd + SSI_GDD_CSDP_REG(lch))); in ssi_gdd_regs_show()
83 readw(gdd + SSI_GDD_CCR_REG(lch))); in ssi_gdd_regs_show()
85 readw(gdd + SSI_GDD_CICR_REG(lch))); in ssi_gdd_regs_show()
87 readw(gdd + SSI_GDD_CSR_REG(lch))); in ssi_gdd_regs_show()
93 readw(gdd + SSI_GDD_CEN_REG(lch))); in ssi_gdd_regs_show()
95 readw(gdd + SSI_GDD_CSAC_REG(lch))); in ssi_gdd_regs_show()
97 readw(gdd + SSI_GDD_CDAC_REG(lch))); in ssi_gdd_regs_show()
99 readw(gdd + SSI_GDD_CLNK_CTRL_REG(lch))); in ssi_gdd_regs_show()
193 csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch)); in ssi_gdd_complete()
/drivers/mmc/host/
Dsdhci-pxav2.c59 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
71 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
75 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
89 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav2_mmc_set_bus_width()

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