Searched refs:ref_clks (Results 1 – 5 of 5) sorted by relevance
932 refclk = dev_priv->dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()942 refclk = dev_priv->dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()1090 i915->dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()1093 i915->dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()1095 i915->dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()1586 i915->dpll.ref_clks.nssc, in skl_ddi_hdmi_pll_dividers()1613 int ref_clock = i915->dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()1820 i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; in skl_update_dpll_ref_clks()2265 return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()2303 i915->dpll.ref_clks.ssc = 100000; in bxt_update_dpll_ref_clks()[all …]
1096 dev_priv->dpll.ref_clks.nssc, in i915_shared_dplls_info()1097 dev_priv->dpll.ref_clks.ssc); in i915_shared_dplls_info()
61 static const struct pic32_ref_osc_data ref_clks[] = { variable217 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core); in pic32mzda_clk_probe()
1014 } ref_clks; member
510 refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc; in bdw_vgpu_get_dp_bitrate()541 int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc; in bxt_vgpu_get_dp_bitrate()