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Searched refs:reset_mask (Results 1 – 25 of 27) sorted by relevance

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/drivers/clk/sunxi/
Dclk-usb.c84 u32 reset_mask; member
141 if (data->reset_mask == 0) in sunxi_usb_clk_setup()
159 reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; in sunxi_usb_clk_setup()
167 .reset_mask = BIT(2) | BIT(1) | BIT(0),
180 .reset_mask = BIT(1) | BIT(0),
191 .reset_mask = BIT(2) | BIT(1) | BIT(0),
202 .reset_mask = BIT(2) | BIT(1) | BIT(0),
214 .reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
225 .reset_mask = BIT(19) | BIT(18) | BIT(17),
239 .reset_mask = BIT(21) | BIT(20) | BIT(19) | BIT(18) | BIT(17),
/drivers/gpu/drm/radeon/
Dni.c1735 u32 reset_mask = 0; in cayman_gpu_check_soft_reset() local
1746 reset_mask |= RADEON_RESET_GFX; in cayman_gpu_check_soft_reset()
1750 reset_mask |= RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1753 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in cayman_gpu_check_soft_reset()
1758 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1763 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1768 reset_mask |= RADEON_RESET_DMA; in cayman_gpu_check_soft_reset()
1771 reset_mask |= RADEON_RESET_DMA1; in cayman_gpu_check_soft_reset()
1776 reset_mask |= RADEON_RESET_RLC; in cayman_gpu_check_soft_reset()
1779 reset_mask |= RADEON_RESET_IH; in cayman_gpu_check_soft_reset()
[all …]
Dr600.c1617 u32 reset_mask = 0; in r600_gpu_check_soft_reset() local
1628 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1635 reset_mask |= RADEON_RESET_GFX; in r600_gpu_check_soft_reset()
1640 reset_mask |= RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1643 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in r600_gpu_check_soft_reset()
1648 reset_mask |= RADEON_RESET_DMA; in r600_gpu_check_soft_reset()
1653 reset_mask |= RADEON_RESET_RLC; in r600_gpu_check_soft_reset()
1656 reset_mask |= RADEON_RESET_IH; in r600_gpu_check_soft_reset()
1659 reset_mask |= RADEON_RESET_SEM; in r600_gpu_check_soft_reset()
1662 reset_mask |= RADEON_RESET_GRBM; in r600_gpu_check_soft_reset()
[all …]
Devergreen.c3829 u32 reset_mask = 0; in evergreen_gpu_check_soft_reset() local
3839 reset_mask |= RADEON_RESET_GFX; in evergreen_gpu_check_soft_reset()
3843 reset_mask |= RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()
3846 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in evergreen_gpu_check_soft_reset()
3851 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()
3856 reset_mask |= RADEON_RESET_DMA; in evergreen_gpu_check_soft_reset()
3861 reset_mask |= RADEON_RESET_RLC; in evergreen_gpu_check_soft_reset()
3864 reset_mask |= RADEON_RESET_IH; in evergreen_gpu_check_soft_reset()
3867 reset_mask |= RADEON_RESET_SEM; in evergreen_gpu_check_soft_reset()
3870 reset_mask |= RADEON_RESET_GRBM; in evergreen_gpu_check_soft_reset()
[all …]
Dsi.c3775 u32 reset_mask = 0; in si_gpu_check_soft_reset() local
3786 reset_mask |= RADEON_RESET_GFX; in si_gpu_check_soft_reset()
3790 reset_mask |= RADEON_RESET_CP; in si_gpu_check_soft_reset()
3793 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP; in si_gpu_check_soft_reset()
3798 reset_mask |= RADEON_RESET_RLC; in si_gpu_check_soft_reset()
3803 reset_mask |= RADEON_RESET_DMA; in si_gpu_check_soft_reset()
3808 reset_mask |= RADEON_RESET_DMA1; in si_gpu_check_soft_reset()
3813 reset_mask |= RADEON_RESET_DMA; in si_gpu_check_soft_reset()
3816 reset_mask |= RADEON_RESET_DMA1; in si_gpu_check_soft_reset()
3822 reset_mask |= RADEON_RESET_IH; in si_gpu_check_soft_reset()
[all …]
Devergreen_dma.c172 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_dma_is_lockup() local
174 if (!(reset_mask & RADEON_RESET_DMA)) { in evergreen_dma_is_lockup()
Dcik.c4844 u32 reset_mask = 0; in cik_gpu_check_soft_reset() local
4855 reset_mask |= RADEON_RESET_GFX; in cik_gpu_check_soft_reset()
4858 reset_mask |= RADEON_RESET_CP; in cik_gpu_check_soft_reset()
4863 reset_mask |= RADEON_RESET_RLC; in cik_gpu_check_soft_reset()
4868 reset_mask |= RADEON_RESET_DMA; in cik_gpu_check_soft_reset()
4873 reset_mask |= RADEON_RESET_DMA1; in cik_gpu_check_soft_reset()
4878 reset_mask |= RADEON_RESET_DMA; in cik_gpu_check_soft_reset()
4881 reset_mask |= RADEON_RESET_DMA1; in cik_gpu_check_soft_reset()
4887 reset_mask |= RADEON_RESET_IH; in cik_gpu_check_soft_reset()
4890 reset_mask |= RADEON_RESET_SEM; in cik_gpu_check_soft_reset()
[all …]
Dsi_dma.c42 u32 reset_mask = si_gpu_check_soft_reset(rdev); in si_dma_is_lockup() local
50 if (!(reset_mask & mask)) { in si_dma_is_lockup()
Dr600_dma.c209 u32 reset_mask = r600_gpu_check_soft_reset(rdev); in r600_dma_is_lockup() local
211 if (!(reset_mask & RADEON_RESET_DMA)) { in r600_dma_is_lockup()
Dni_dma.c288 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_dma_is_lockup() local
296 if (!(reset_mask & mask)) { in cayman_dma_is_lockup()
Dcik_sdma.c776 u32 reset_mask = cik_gpu_check_soft_reset(rdev); in cik_sdma_is_lockup() local
784 if (!(reset_mask & mask)) { in cik_sdma_is_lockup()
/drivers/reset/
Dreset-ti-sci.c33 u32 reset_mask; member
91 reset_state |= control->reset_mask; in ti_sci_reset_set()
93 reset_state &= ~control->reset_mask; in ti_sci_reset_set()
169 return reset_state & control->reset_mask; in ti_sci_reset_status()
206 control->reset_mask = reset_spec->args[1]; in ti_sci_reset_of_xlate()
/drivers/gpu/drm/i915/gt/
Dintel_gt_pm_irq.c61 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask) in gen6_gt_pm_reset_iir() argument
68 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
69 intel_uncore_write(uncore, reg, reset_mask); in gen6_gt_pm_reset_iir()
Dintel_reset.c417 u32 *reset_mask, in gen11_lock_sfc() argument
504 *reset_mask |= sfc_lock.reset_bit; in gen11_lock_sfc()
549 u32 reset_mask, unlock_mask = 0; in __gen11_reset_engines() local
553 reset_mask = GEN11_GRDOM_FULL; in __gen11_reset_engines()
555 reset_mask = 0; in __gen11_reset_engines()
558 reset_mask |= hw_engine_mask[engine->id]; in __gen11_reset_engines()
559 ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask); in __gen11_reset_engines()
565 ret = gen6_hw_domain_reset(gt, reset_mask); in __gen11_reset_engines()
Dintel_gt_pm_irq.h19 void gen6_gt_pm_reset_iir(struct intel_gt *gt, u32 reset_mask);
/drivers/clk/
Dclk-twl6040.c33 const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */ in twl6040_pdmclk_reset_one_clock() local
36 ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
40 ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask); in twl6040_pdmclk_reset_one_clock()
/drivers/misc/cxl/
Dhcalls.c439 u64 control_mask, u64 reset_mask) in cxl_h_control_faults() argument
448 control_mask, reset_mask); in cxl_h_control_faults()
450 unit_address, process_token, control_mask, reset_mask, in cxl_h_control_faults()
453 control_mask, reset_mask, retbuf[0], rc); in cxl_h_control_faults()
Dtrace.h610 u64 control_mask, u64 reset_mask, unsigned long r4,
614 control_mask, reset_mask, r4, rc),
620 __field(u64, reset_mask)
629 __entry->reset_mask = reset_mask;
639 __entry->reset_mask,
Dhcalls.h168 u64 control_mask, u64 reset_mask);
/drivers/net/ethernet/ibm/
Dibmveth.h73 unsigned long reset_mask, unsigned long set_mask, in h_illan_attributes() argument
80 reset_mask, set_mask); in h_illan_attributes()
/drivers/crypto/qat/qat_common/
Dqat_hal.c304 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_reset() local
309 csr_val |= reset_mask; in qat_hal_reset()
476 unsigned int reset_mask = handle->chip_info->icp_rst_mask; in qat_hal_clr_reset() local
485 csr_val &= ~reset_mask; in qat_hal_clr_reset()
491 csr_val &= reset_mask; in qat_hal_clr_reset()
495 csr_val |= reset_mask; in qat_hal_clr_reset()
/drivers/net/ethernet/smsc/
Dsmsc911x.c1449 unsigned int reset_mask = HW_CFG_SRST_; in smsc911x_soft_reset() local
1479 reset_mask = RESET_CTL_DIGITAL_RST_; in smsc911x_soft_reset()
1483 smsc911x_reg_write(pdata, reset_offset, reset_mask); in smsc911x_soft_reset()
1490 } while ((--timeout) && (temp & reset_mask)); in smsc911x_soft_reset()
1492 if (unlikely(temp & reset_mask)) { in smsc911x_soft_reset()
/drivers/net/wireless/ath/ath10k/
Dhw.h297 u32 reset_mask; member
Dhw.c369 .reset_mask = 0xffffffff,
/drivers/net/ethernet/3com/
D3c59x.c1941 int do_tx_reset = 0, reset_mask = 0; in vortex_error() local
1969 reset_mask = 0x0108; /* Reset interface logic, but not download logic */ in vortex_error()
2033 issue_and_wait(dev, TxReset|reset_mask); in vortex_error()

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