| /drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| D | user.c | 311 const struct nvkm_device_oclass *sclass = oclass->priv; in nvkm_udevice_child_new() local
312 return sclass->ctor(udev->device, oclass, data, size, pobject); in nvkm_udevice_child_new()
326 const struct nvkm_device_oclass *sclass = NULL; in nvkm_udevice_child_get() local
329 for (; i = __ffs64(mask), mask && !sclass; mask &= ~(1ULL << i)) { in nvkm_udevice_child_get()
331 !(engine->func->base.sclass)) in nvkm_udevice_child_get()
335 index -= engine->func->base.sclass(oclass, index, &sclass); in nvkm_udevice_child_get()
338 if (!sclass) { in nvkm_udevice_child_get()
340 sclass = &nvkm_control_oclass; in nvkm_udevice_child_get()
342 sclass = &device->mmu->user; in nvkm_udevice_child_get()
344 sclass = &device->fault->user; in nvkm_udevice_child_get()
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| /drivers/gpu/drm/nouveau/nvif/ |
| D | object.c | 62 struct nvif_ioctl_sclass_v0 sclass; in nvif_object_sclass_get() member
68 size = sizeof(*args) + cnt * sizeof(args->sclass.oclass[0]); in nvif_object_sclass_get()
73 args->sclass.version = 0; in nvif_object_sclass_get()
74 args->sclass.count = cnt; in nvif_object_sclass_get()
77 if (ret == 0 && args->sclass.count <= cnt) in nvif_object_sclass_get()
79 cnt = args->sclass.count; in nvif_object_sclass_get()
85 *psclass = kcalloc(args->sclass.count, sizeof(**psclass), GFP_KERNEL); in nvif_object_sclass_get()
87 for (i = 0; i < args->sclass.count; i++) { in nvif_object_sclass_get()
88 (*psclass)[i].oclass = args->sclass.oclass[i].oclass; in nvif_object_sclass_get()
89 (*psclass)[i].minver = args->sclass.oclass[i].minver; in nvif_object_sclass_get()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | channv50.c | 250 const struct nvkm_device_oclass *sclass = oclass->priv; in nv50_disp_chan_child_new() local
260 ret = sclass->ctor(device, oclass, argv, argc, &object->oproxy.object); in nv50_disp_chan_child_new()
274 struct nvkm_oclass *sclass) in nv50_disp_chan_child_get() argument
281 sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ, 0); in nv50_disp_chan_child_get()
283 sclass->engine = NULL; in nv50_disp_chan_child_get()
285 if (sclass->engine && sclass->engine->func->base.sclass) { in nv50_disp_chan_child_get()
286 sclass->engine->func->base.sclass(sclass, index, &oclass); in nv50_disp_chan_child_get()
288 sclass->ctor = nv50_disp_chan_child_new, in nv50_disp_chan_child_get()
289 sclass->priv = oclass; in nv50_disp_chan_child_get()
334 .sclass = nv50_disp_chan_child_get,
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| D | rootnv50.c | 287 struct nvkm_oclass *sclass) in nv50_disp_root_child_get_() argument
292 sclass->base = root->func->user[index].base; in nv50_disp_root_child_get_()
293 sclass->priv = root->func->user + index; in nv50_disp_root_child_get_()
294 sclass->ctor = nv50_disp_root_child_new_; in nv50_disp_root_child_get_()
313 .sclass = nv50_disp_root_child_get_,
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| /drivers/gpu/drm/nouveau/nvkm/engine/sw/ |
| D | base.c | 54 const struct nvkm_sw_chan_sclass *sclass = oclass->engn; in nvkm_sw_oclass_new() local
55 return sclass->ctor(chan, oclass, data, size, pobject); in nvkm_sw_oclass_new()
64 while (sw->func->sclass[c].ctor) { in nvkm_sw_oclass_get()
66 oclass->engn = &sw->func->sclass[index]; in nvkm_sw_oclass_get()
67 oclass->base = sw->func->sclass[index].base; in nvkm_sw_oclass_get()
95 .fifo.sclass = nvkm_sw_oclass_get,
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| /drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| D | base.c | 67 nvkm_dma_oclass_base_get(struct nvkm_oclass *sclass, int index, in nvkm_dma_oclass_base_get() argument
73 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
74 sclass->engn = oclass; in nvkm_dma_oclass_base_get()
101 .base.sclass = nvkm_dma_oclass_base_get,
102 .fifo.sclass = nvkm_dma_oclass_fifo_get,
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_abi16.c | 432 struct nvif_sclass *sclass; in nouveau_abi16_ioctl_grobj_alloc() local
447 ret = nvif_object_sclass_get(&chan->chan->user, &sclass); in nouveau_abi16_ioctl_grobj_alloc()
454 switch (sclass[i].oclass) { in nouveau_abi16_ioctl_grobj_alloc()
459 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
469 if ((sclass[i].oclass & 0x00ff) == 0x00b1) { in nouveau_abi16_ioctl_grobj_alloc()
470 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
478 if ((sclass[i].oclass & 0x00ff) == 0x00b2) { in nouveau_abi16_ioctl_grobj_alloc()
479 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
487 if ((sclass[i].oclass & 0x00ff) == 0x00b3) { in nouveau_abi16_ioctl_grobj_alloc()
488 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
[all …]
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| /drivers/gpu/drm/nouveau/include/nvif/ |
| D | object.h | 81 struct nvif_sclass *sclass; \
86 cnt = nvif_object_sclass_get(object, &sclass); \
90 if (mclass[i].oclass == sclass[j].oclass && \
91 mclass[i].version >= sclass[j].minver && \
92 mclass[i].version <= sclass[j].maxver) { \
98 nvif_object_sclass_put(&sclass); \
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| /drivers/gpu/drm/nouveau/include/nvkm/core/ |
| D | engine.h | 35 int (*sclass)(struct nvkm_oclass *, int index, member
43 int (*sclass)(struct nvkm_oclass *, int index); member
47 struct nvkm_sclass sclass[]; member
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | base.c | 237 const struct nvkm_fifo_chan_oclass *sclass = oclass->engn; in nvkm_fifo_class_new() local
239 return sclass->ctor(fifo, oclass, data, size, pobject); in nvkm_fifo_class_new()
252 const struct nvkm_fifo_chan_oclass *sclass; in nvkm_fifo_class_get() local
262 while ((sclass = fifo->func->chan[c])) { in nvkm_fifo_class_get()
264 oclass->base = sclass->base; in nvkm_fifo_class_get()
265 oclass->engn = sclass; in nvkm_fifo_class_get()
350 .base.sclass = nvkm_fifo_class_get,
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| D | chan.c | 225 if (engine->func->fifo.sclass) { in nvkm_fifo_chan_child_get()
226 ret = engine->func->fifo.sclass(oclass, index); in nvkm_fifo_chan_child_get()
238 while (engine->func->sclass[c].oclass) { in nvkm_fifo_chan_child_get()
240 oclass->base = engine->func->sclass[index]; in nvkm_fifo_chan_child_get()
357 .sclass = nvkm_fifo_chan_child_get,
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| /drivers/gpu/drm/nouveau/nvkm/core/ |
| D | client.c | 241 const struct nvkm_sclass *sclass; in nvkm_client_child_get() local
244 case 0: sclass = &nvkm_uclient_sclass; break; in nvkm_client_child_get()
245 case 1: sclass = &nvkm_udevice_sclass; break; in nvkm_client_child_get()
251 oclass->base = *sclass; in nvkm_client_child_get()
282 .sclass = nvkm_client_child_get,
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| D | oproxy.c | 103 if (!oproxy->object->func->sclass) in nvkm_oproxy_sclass()
105 return oproxy->object->func->sclass(oproxy->object, index, oclass); in nvkm_oproxy_sclass()
190 .sclass = nvkm_oproxy_sclass,
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| D | ioctl.c | 66 while (object->func->sclass && in nvkm_ioctl_sclass()
67 object->func->sclass(object, i, &oclass) >= 0) { in nvkm_ioctl_sclass()
102 if (!parent->func->sclass) { in nvkm_ioctl_new()
115 ret = parent->func->sclass(parent, i++, &oclass); in nvkm_ioctl_new()
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| /drivers/gpu/drm/nouveau/nvkm/engine/ce/ |
| D | gf100.c | 43 .sclass = {
57 .sclass = {
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| D | gm200.c | 31 .sclass = {
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| D | tu102.c | 29 .sclass = {
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| D | gv100.c | 29 .sclass = {
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | base.c | 101 while (gr->func->sclass[c].oclass) { in nvkm_gr_oclass_get()
103 oclass->base = gr->func->sclass[index]; in nvkm_gr_oclass_get()
173 .fifo.sclass = nvkm_gr_oclass_get,
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| /drivers/gpu/drm/nouveau/nvkm/engine/ |
| D | xtensa.c | 33 while (xtensa->func->sclass[c].oclass) { in nvkm_xtensa_oclass_get()
35 oclass->base = xtensa->func->sclass[index]; in nvkm_xtensa_oclass_get()
173 .fifo.sclass = nvkm_xtensa_oclass_get,
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| /drivers/gpu/drm/nouveau/nvkm/engine/msppp/ |
| D | gt215.c | 31 .sclass = {
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| /drivers/gpu/drm/nouveau/nvkm/engine/mspdec/ |
| D | gk104.c | 31 .sclass = {
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| /drivers/gpu/drm/nouveau/nvkm/engine/msvld/ |
| D | gk104.c | 31 .sclass = {
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| D | gt215.c | 31 .sclass = {
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| /drivers/gpu/drm/nouveau/nvkm/engine/vp/ |
| D | g84.c | 32 .sclass = {
|