| /drivers/clk/ti/ |
| D | dpll.c | 37 .set_rate = &omap3_noncore_dpll_set_rate,
62 .set_rate = &omap3_noncore_dpll_set_rate,
75 .set_rate = &omap3_noncore_dpll_set_rate,
94 .set_rate = &omap2_reprogram_dpllcore,
116 .set_rate = &omap3_noncore_dpll_set_rate,
128 .set_rate = &omap3_dpll5_set_rate,
140 .set_rate = &omap3_dpll4_set_rate,
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| /drivers/clk/actions/ |
| D | owl-composite.c | 157 .set_rate = owl_comp_div_set_rate,
174 .set_rate = owl_comp_fact_set_rate,
186 .set_rate = owl_comp_fix_fact_set_rate,
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| /drivers/sh/clk/ |
| D | cpg.c | 182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
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| D | core.c | 490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
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| /drivers/clk/ |
| D | clk-composite.c | 140 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
160 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
164 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
262 if (rate_ops->set_rate) { in __clk_hw_register_composite()
264 clk_composite_ops->set_rate = in __clk_hw_register_composite()
276 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
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| /drivers/clk/mvebu/ |
| D | clk-corediv.c | 203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
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| /drivers/clk/mxs/ |
| D | clk-div.c | 57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
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| /drivers/clk/samsung/ |
| D | clk-pll.c | 297 .set_rate = samsung_pll35xx_set_rate,
408 .set_rate = samsung_pll36xx_set_rate,
533 .set_rate = samsung_pll45xx_set_rate,
678 .set_rate = samsung_pll46xx_set_rate,
907 .set_rate = samsung_s3c2410_pll_set_rate,
915 .set_rate = samsung_s3c2410_pll_set_rate,
923 .set_rate = samsung_s3c2410_pll_set_rate,
1054 .set_rate = samsung_pll2550xx_set_rate,
1146 .set_rate = samsung_pll2650x_set_rate,
1236 .set_rate = samsung_pll2650xx_set_rate,
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| /drivers/clk/tegra/ |
| D | clk-periph.c | 69 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
134 .set_rate = clk_periph_set_rate,
157 .set_rate = clk_periph_set_rate,
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| D | clk-tegra-super-cclk.c | 46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
112 .set_rate = cclk_super_set_rate,
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| /drivers/clk/ux500/ |
| D | clk-prcmu.c | 197 .set_rate = clk_prcmu_set_rate,
214 .set_rate = clk_prcmu_set_rate,
241 .set_rate = clk_prcmu_set_rate,
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| /drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 921 .set_rate = clk_alpha_pll_set_rate,
931 .set_rate = alpha_pll_huayra_set_rate,
941 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1036 .set_rate = clk_alpha_pll_postdiv_set_rate,
1277 .set_rate = alpha_pll_fabia_set_rate,
1372 .set_rate = clk_trion_pll_postdiv_set_rate,
1418 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1570 .set_rate = alpha_pll_trion_set_rate,
1581 .set_rate = alpha_pll_trion_set_rate,
1588 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
[all …]
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| D | clk-rcg2.c | 454 .set_rate = clk_rcg2_set_rate,
467 .set_rate = clk_rcg2_set_floor_rate,
595 .set_rate = clk_edp_pixel_set_rate,
653 .set_rate = clk_byte_set_rate,
723 .set_rate = clk_byte2_set_rate,
814 .set_rate = clk_pixel_set_rate,
919 .set_rate = clk_gfx3d_set_rate,
1058 .set_rate = clk_rcg2_shared_set_rate,
1320 .set_rate = clk_rcg2_dp_set_rate,
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| D | clk-rcg.c | 815 .set_rate = clk_rcg_set_rate,
826 .set_rate = clk_rcg_bypass_set_rate,
837 .set_rate = clk_rcg_bypass2_set_rate,
849 .set_rate = clk_rcg_pixel_set_rate,
861 .set_rate = clk_rcg_esc_set_rate,
873 .set_rate = clk_rcg_lcc_set_rate,
885 .set_rate = clk_dyn_rcg_set_rate,
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| /drivers/clk/st/ |
| D | clk-flexgen.c | 184 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
185 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
187 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
188 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
202 .set_rate = flexgen_set_rate,
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| /drivers/clk/imx/ |
| D | clk-pllv3.c | 155 .set_rate = clk_pllv3_set_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
299 .set_rate = clk_pllv3_av_set_rate,
392 .set_rate = clk_pllv3_vf610_set_rate,
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| D | clk-busy.c | 63 ret = busy->div_ops->set_rate(&busy->div.hw, rate, parent_rate); in clk_busy_divider_set_rate()
73 .set_rate = clk_busy_divider_set_rate,
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| D | clk-scu.c | 429 .set_rate = clk_scu_set_rate,
439 .set_rate = clk_scu_atf_set_cpu_rate,
447 .set_rate = clk_scu_set_rate,
760 .set_rate = clk_gpr_div_scu_set_rate,
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| /drivers/clk/at91/ |
| D | clk-usb.c | 156 .set_rate = at91sam9x5_clk_usb_set_rate,
192 .set_rate = at91sam9x5_clk_usb_set_rate,
361 .set_rate = at91rm9200_clk_usb_set_rate,
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| D | clk-audio-pll.c | 432 .set_rate = clk_audio_pll_frac_set_rate,
440 .set_rate = clk_audio_pll_pad_set_rate,
448 .set_rate = clk_audio_pll_pmc_set_rate,
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| D | clk-sam9x60-pll.c | 289 .set_rate = sam9x60_frac_pll_set_rate,
298 .set_rate = sam9x60_frac_pll_set_rate_chg,
491 .set_rate = sam9x60_div_pll_set_rate,
500 .set_rate = sam9x60_div_pll_set_rate_chg,
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| /drivers/clk/baikal-t1/ |
| D | ccu-div.c | 557 .set_rate = ccu_div_var_set_rate_fast,
564 .set_rate = ccu_div_var_set_rate_slow,
574 .set_rate = ccu_div_fixed_set_rate,
588 .set_rate = ccu_div_fixed_set_rate,
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| /drivers/staging/clocking-wizard/ |
| D | TODO | 4 - support for set_rate() operations (may benefit from Stephen Boyd's
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| /drivers/clk/sifive/ |
| D | fu540-prci.c | 48 .set_rate = sifive_prci_wrpll_set_rate,
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| /drivers/clk/sprd/ |
| D | composite.c | 58 .set_rate = sprd_comp_set_rate,
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