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Searched refs:sps (Results 1 – 24 of 24) sorted by relevance

/drivers/media/platform/allegro-dvt/
Dnal-h264.c272 static void nal_h264_rbsp_sps(struct rbsp *rbsp, struct nal_h264_sps *sps) in nal_h264_rbsp_sps() argument
276 if (!sps) { in nal_h264_rbsp_sps()
281 rbsp_bits(rbsp, 8, &sps->profile_idc); in nal_h264_rbsp_sps()
282 rbsp_bit(rbsp, &sps->constraint_set0_flag); in nal_h264_rbsp_sps()
283 rbsp_bit(rbsp, &sps->constraint_set1_flag); in nal_h264_rbsp_sps()
284 rbsp_bit(rbsp, &sps->constraint_set2_flag); in nal_h264_rbsp_sps()
285 rbsp_bit(rbsp, &sps->constraint_set3_flag); in nal_h264_rbsp_sps()
286 rbsp_bit(rbsp, &sps->constraint_set4_flag); in nal_h264_rbsp_sps()
287 rbsp_bit(rbsp, &sps->constraint_set5_flag); in nal_h264_rbsp_sps()
288 rbsp_bits(rbsp, 2, &sps->reserved_zero_2bits); in nal_h264_rbsp_sps()
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Dnal-hevc.c280 static void nal_hevc_rbsp_sps(struct rbsp *rbsp, struct nal_hevc_sps *sps) in nal_hevc_rbsp_sps() argument
284 rbsp_bits(rbsp, 4, &sps->video_parameter_set_id); in nal_hevc_rbsp_sps()
285 rbsp_bits(rbsp, 3, &sps->max_sub_layers_minus1); in nal_hevc_rbsp_sps()
286 rbsp_bit(rbsp, &sps->temporal_id_nesting_flag); in nal_hevc_rbsp_sps()
287 nal_hevc_rbsp_profile_tier_level(rbsp, &sps->profile_tier_level); in nal_hevc_rbsp_sps()
288 rbsp_uev(rbsp, &sps->seq_parameter_set_id); in nal_hevc_rbsp_sps()
290 rbsp_uev(rbsp, &sps->chroma_format_idc); in nal_hevc_rbsp_sps()
291 if (sps->chroma_format_idc == 3) in nal_hevc_rbsp_sps()
292 rbsp_bit(rbsp, &sps->separate_colour_plane_flag); in nal_hevc_rbsp_sps()
293 rbsp_uev(rbsp, &sps->pic_width_in_luma_samples); in nal_hevc_rbsp_sps()
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Dallegro-core.c1494 struct nal_h264_sps *sps; in allegro_h264_write_sps() local
1505 sps = kzalloc(sizeof(*sps), GFP_KERNEL); in allegro_h264_write_sps()
1506 if (!sps) in allegro_h264_write_sps()
1512 sps->profile_idc = nal_h264_profile_from_v4l2(profile); in allegro_h264_write_sps()
1513 sps->constraint_set0_flag = 0; in allegro_h264_write_sps()
1514 sps->constraint_set1_flag = 1; in allegro_h264_write_sps()
1515 sps->constraint_set2_flag = 0; in allegro_h264_write_sps()
1516 sps->constraint_set3_flag = 0; in allegro_h264_write_sps()
1517 sps->constraint_set4_flag = 0; in allegro_h264_write_sps()
1518 sps->constraint_set5_flag = 0; in allegro_h264_write_sps()
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Dnal-h264.h194 void *dest, size_t n, struct nal_h264_sps *sps);
196 struct nal_h264_sps *sps, void *src, size_t n);
197 void nal_h264_print_sps(const struct device *dev, struct nal_h264_sps *sps);
Dnal-hevc.h338 void *dest, size_t n, struct nal_hevc_sps *sps);
340 struct nal_hevc_sps *sps, void *src, size_t n);
/drivers/media/platform/coda/
Dcoda-h264.c259 struct rbsp sps; in coda_h264_sps_fixup() local
266 sps.buf = buf + 5; /* Skip NAL header */ in coda_h264_sps_fixup()
267 sps.size = *size - 5; in coda_h264_sps_fixup()
269 profile_idc = sps.buf[0]; in coda_h264_sps_fixup()
272 sps.pos = 24; in coda_h264_sps_fixup()
275 ret = rbsp_read_uev(&sps, NULL); in coda_h264_sps_fixup()
291 ret = rbsp_read_uev(&sps, NULL); in coda_h264_sps_fixup()
295 ret = rbsp_read_uev(&sps, &pic_order_cnt_type); in coda_h264_sps_fixup()
301 ret = rbsp_read_uev(&sps, NULL); in coda_h264_sps_fixup()
308 ret = rbsp_read_bit(&sps); in coda_h264_sps_fixup()
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/drivers/soc/actions/
Dowl-sps.c44 struct owl_sps *sps; member
54 return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable); in owl_sps_set_power()
61 dev_dbg(pd->sps->dev, "%s power on", pd->info->name); in owl_sps_power_on()
70 dev_dbg(pd->sps->dev, "%s power off", pd->info->name); in owl_sps_power_off()
75 static int owl_sps_init_domain(struct owl_sps *sps, int index) in owl_sps_init_domain() argument
79 pd = devm_kzalloc(sps->dev, sizeof(*pd), GFP_KERNEL); in owl_sps_init_domain()
83 pd->info = &sps->info->domains[index]; in owl_sps_init_domain()
84 pd->sps = sps; in owl_sps_init_domain()
92 sps->genpd_data.domains[index] = &pd->genpd; in owl_sps_init_domain()
101 struct owl_sps *sps; in owl_sps_probe() local
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DMakefile3 obj-$(CONFIG_OWL_PM_DOMAINS_HELPER) += owl-sps-helper.o
4 obj-$(CONFIG_OWL_PM_DOMAINS) += owl-sps.o
/drivers/staging/media/hantro/
Dhantro_g2_hevc_dec.c30 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps; in prepare_tile_info_buffer() local
44 max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 + in prepare_tile_info_buffer()
45 sps->log2_diff_max_min_luma_coding_block_size; in prepare_tile_info_buffer()
46 pic_width_in_ctbs = (sps->pic_width_in_luma_samples + in prepare_tile_info_buffer()
48 pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 << max_log2_ctb_size) - 1) in prepare_tile_info_buffer()
123 const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps; in set_params() local
132 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8); in set_params()
133 hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8); in set_params()
139 min_log2_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3; in set_params()
140 max_log2_ctb_size = min_log2_cb_size + sps->log2_diff_max_min_luma_coding_block_size; in set_params()
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Dhantro_hevc.c30 size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps) in hantro_hevc_chroma_offset() argument
32 int bytes_per_pixel = sps->bit_depth_luma_minus8 == 0 ? 1 : 2; in hantro_hevc_chroma_offset()
34 return sps->pic_width_in_luma_samples * in hantro_hevc_chroma_offset()
35 sps->pic_height_in_luma_samples * bytes_per_pixel; in hantro_hevc_chroma_offset()
38 size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps) in hantro_hevc_motion_vectors_offset() argument
40 size_t cr_offset = hantro_hevc_chroma_offset(sps); in hantro_hevc_motion_vectors_offset()
45 static size_t hantro_hevc_mv_size(const struct v4l2_ctrl_hevc_sps *sps) in hantro_hevc_mv_size() argument
47 u32 min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; in hantro_hevc_mv_size()
48 u32 ctb_log2_size_y = min_cb_log2_size_y + sps->log2_diff_max_min_luma_coding_block_size; in hantro_hevc_mv_size()
49 u32 pic_width_in_ctbs_y = (sps->pic_width_in_luma_samples + (1 << ctb_log2_size_y) - 1) in hantro_hevc_mv_size()
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Dhantro_g1_h264_dec.c26 const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; in set_params() local
33 if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) in set_params()
35 if (sps->profile_idc > 66) { in set_params()
41 if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && in set_params()
42 (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || in set_params()
54 G1_REG_DEC_CTRL1_REF_FRAMES(sps->max_num_ref_frames); in set_params()
63 if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) in set_params()
74 reg = G1_REG_DEC_CTRL4_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | in set_params()
79 if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) in set_params()
81 if (sps->profile_idc >= 100 && sps->chroma_format_idc == 0) in set_params()
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Drockchip_vpu2_hw_h264_dec.c197 const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; in set_params() local
238 VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && in set_params()
239 (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || in set_params()
243 VDPU_REG_WRITE_MVS_E((sps->profile_idc > 66) && dec_param->nal_ref_idc) | in set_params()
244 VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | in set_params()
245 VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) | in set_params()
268 VDPU_REG_REF_FRAMES(sps->max_num_ref_frames); in set_params()
273 VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | in set_params()
288 VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | in set_params()
289 VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | in set_params()
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Dhantro_hw.h68 const struct v4l2_ctrl_h264_sps *sps; member
115 const struct v4l2_ctrl_hevc_sps *sps; member
257 size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps);
258 size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps);
Dhantro_drv.c246 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; in hantro_try_ctrl() local
248 if (sps->chroma_format_idc > 1) in hantro_try_ctrl()
251 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) in hantro_try_ctrl()
254 if (sps->bit_depth_luma_minus8 != 0) in hantro_try_ctrl()
258 const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; in hantro_try_ctrl() local
260 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) in hantro_try_ctrl()
263 if (sps->bit_depth_luma_minus8 != 0) in hantro_try_ctrl()
266 if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED) in hantro_try_ctrl()
Dhantro_h264.c378 ctrls->sps = in hantro_h264_dec_prepare_run()
380 if (WARN_ON(!ctrls->sps)) in hantro_h264_dec_prepare_run()
396 ctrls->sps, ctx->h264_dec.dpb); in hantro_h264_dec_prepare_run()
/drivers/staging/media/sunxi/cedrus/
Dcedrus_h265.c249 const struct v4l2_ctrl_hevc_sps *sps; in cedrus_h265_setup() local
263 sps = run->h265.sps; in cedrus_h265_setup()
270 sps->log2_min_luma_coding_block_size_minus3 + 3 + in cedrus_h265_setup()
271 sps->log2_diff_max_min_luma_coding_block_size; in cedrus_h265_setup()
274 DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); in cedrus_h265_setup()
359 …reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_dep… in cedrus_h265_setup()
360 …VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_int… in cedrus_h265_setup()
361 …VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transfo… in cedrus_h265_setup()
362 …VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_si… in cedrus_h265_setup()
363 …VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_codin… in cedrus_h265_setup()
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Dcedrus_h264.c98 const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; in cedrus_write_frame_list() local
151 else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) in cedrus_write_frame_list()
327 const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; in cedrus_set_params() local
403 reg |= (sps->chroma_format_idc & 0x7) << 19; in cedrus_set_params()
404 reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; in cedrus_set_params()
405 reg |= sps->pic_height_in_map_units_minus1 & 0xff; in cedrus_set_params()
406 if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) in cedrus_set_params()
408 if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) in cedrus_set_params()
410 if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) in cedrus_set_params()
415 (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); in cedrus_set_params()
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Dcedrus_dec.c60 run.h264.sps = cedrus_find_control_data(ctx, in cedrus_device_run()
67 run.h265.sps = cedrus_find_control_data(ctx, in cedrus_device_run()
Dcedrus.h66 const struct v4l2_ctrl_h264_sps *sps; member
77 const struct v4l2_ctrl_hevc_sps *sps; member
/drivers/staging/media/rkvdec/
Drkvdec-h264.c112 const struct v4l2_ctrl_h264_sps *sps; member
640 const struct v4l2_ctrl_h264_sps *sps = run->sps; in assemble_hw_pps() local
664 WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); in assemble_hw_pps()
665 WRITE_PPS(sps->bit_depth_luma_minus8, BIT_DEPTH_LUMA); in assemble_hw_pps()
666 WRITE_PPS(sps->bit_depth_chroma_minus8, BIT_DEPTH_CHROMA); in assemble_hw_pps()
668 WRITE_PPS(sps->log2_max_frame_num_minus4, LOG2_MAX_FRAME_NUM_MINUS4); in assemble_hw_pps()
669 WRITE_PPS(sps->max_num_ref_frames, MAX_NUM_REF_FRAMES); in assemble_hw_pps()
670 WRITE_PPS(sps->pic_order_cnt_type, PIC_ORDER_CNT_TYPE); in assemble_hw_pps()
671 WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4, in assemble_hw_pps()
673 WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO), in assemble_hw_pps()
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Drkvdec.c33 const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; in rkvdec_try_ctrl() local
39 if (sps->chroma_format_idc > 1) in rkvdec_try_ctrl()
42 if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) in rkvdec_try_ctrl()
45 if (sps->bit_depth_luma_minus8 != 0) in rkvdec_try_ctrl()
/drivers/iio/imu/
Dadis16400.c349 int sps, ret; in adis16400_get_freq() local
356 sps = (t & ADIS16400_SMPL_PRD_TIME_BASE) ? 52851 : 1638404; in adis16400_get_freq()
357 sps /= (t & ADIS16400_SMPL_PRD_DIV_MASK) + 1; in adis16400_get_freq()
359 return sps; in adis16400_get_freq()
398 static int __adis16400_set_filter(struct iio_dev *indio_dev, int sps, int val) in __adis16400_set_filter() argument
405 if (sps / adis16400_3db_divisors[i] >= val) in __adis16400_set_filter()
500 int ret, sps; in adis16400_write_raw() local
515 sps = st->variant->get_freq(st); in adis16400_write_raw()
516 if (sps < 0) { in adis16400_write_raw()
518 return sps; in adis16400_write_raw()
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/drivers/media/v4l2-core/
Dv4l2-h264.c27 const struct v4l2_ctrl_h264_sps *sps, in v4l2_h264_init_reflist_builder() argument
33 max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4); in v4l2_h264_init_reflist_builder()
/drivers/mtd/nand/raw/
Dmtk_nand.c1221 static int mtk_nfc_set_spare_per_sector(u32 *sps, struct mtd_info *mtd) in mtk_nfc_set_spare_per_sector() argument
1229 *sps = mtd->oobsize / eccsteps; in mtk_nfc_set_spare_per_sector()
1232 *sps >>= 1; in mtk_nfc_set_spare_per_sector()
1234 if (*sps < MTK_NFC_MIN_SPARE) in mtk_nfc_set_spare_per_sector()
1238 if (*sps >= spare[i] && spare[i] >= spare[closest_spare]) { in mtk_nfc_set_spare_per_sector()
1240 if (*sps == spare[i]) in mtk_nfc_set_spare_per_sector()
1245 *sps = spare[closest_spare]; in mtk_nfc_set_spare_per_sector()
1248 *sps <<= 1; in mtk_nfc_set_spare_per_sector()